Mitsubishi Denki Kabushiki Kaisha

Itsuko Kinoshita

Masayuki Hata

Mitsugu Satou

Akitoshi Osaki

A memory system, wherein the respective byte memories 1 to 4 is configured so that data of word unit which are the targets of the parity calculation done by the parity calculation circuits 5 to 8 occupy respectively the same bit positions as those of the 4-word data of word unit, is provided with multiplexers 41 to 44 for connecting selectively to the data bus 29 the bit positions of the data of word unit selected by the word select control circuit 23 in such byte memories 1 to 4. The memory system is capable of improving the flexibility of the memory configuration by being eased of the limitation of the arrangement of bits which are the targets of parity calculation, and reducing the occupied areas of the write/read circuit on a chip as well as the electric power consumption.

Memory system and cache memory system

A clock generator which is provided with a circuit generating non-overlap clock from input clock, a frequency dividing circuit driven by the non-overlap clock and a latch disposed between the frequency dividing circuit and a clock driver, and whose critical pass being a cause of delay is shortened by sampling the frequency-divided output into the latch by the input clock and thereafter driving it by the clock driver, and a clock generator in which an internal clock at high speed in the internal clock logical value generating circuit is added with internal clock edge generating circuit required to operate at high speed and an output of initial stage of a buffer for inputting external clock is divided to supply to the internal clock edge generating circuit and to the other circuits, thereby capacity of the buffer required to operate at high speed in the circuit is decreased to reduce the delay of external clock.

Growing community of inventors

Itami, Japan

Itsuko Kinoshita