Marvell Israel (misl) Ltd.

Nxp Usa, Inc.

Itay Peled

Rami Zemach

Jacob Jul Schroder

Zvi Shmilovici Leib

Dan Ilan

Gideon Navon

Michael Weiner

Moshe Anschel

Gil Levy

David Melman

Eitan Joshua

Eran Rotem

Adar Peery

Amit Gur

Alon Eldar

Shai Koren

Roy Glasner

Fabrice Aidan

Ayal Lior

Rotem Porat

Dmitry Lachover

Joergen P R Hofman-Bang

Einat Ophir

Galia Peleg

Avi Gal

Noam Eshel-Goldman

Joergen Pr Hofman-Bang

Avin Faldu

A network device transfers packets from a packet memory to one or more network interfaces for transmission by the one or more network interfaces. The transferring of packets includes transferring the packets via one or more respective transmit data paths that correspond to one or more respective network interfaces. The network device measures one or more respective amounts of time required to transmit respective packet data within the one or more respective transmit data paths. The network device uses the one or more respective measured amounts of time to determine when to start transfer of packets from the packet memory to the one or more network interfaces via the one or more respective transmit data paths.

Method and apparatus for scheduling packets for transmission

In a network switching system that comprises a plurality of interconnected network devices, a first network device transmits one or more first packets via a first network interface of the first network device, the one or more first packets belonging to a packet flow. The first network device receives a message that indicates congestion corresponding to the packet flow within the network switching system. In response to the message, the first network device selects a second network interface of the first network device for transmitting one or more second packets that belong to the packet flow. After receiving the message, the first network device transmits the one or more second packets via the second network interface of the first network device.

Notification-based load balancing in a network

A search engine of a network device performs a lookup based on packet information associated with a packet being processed using a plurality of packet processing applications. The lookup includes one or more accesses to a lookup table that includes a plurality of interleaved entries associated with different ones of the packet processing applications. For each access, the search engine generates a search key to include at least a search string generated based on the packet information and an application identifier indicating a packet processing application for which the lookup is being performed, identifies an entry based on the search key, determines whether the search key matches search information in the identified entry, and when the search key matches the search information in the identified entry, identifies an action to be performed by the packet processor in connection with processing the packet by the packet processing application.

Interleaved exact-match lookup table for multiple packet processing applications in a network device

A network device comprises a receive processor configured to generate respective packet descriptors that include i) respective header information extracted from headers of packets received via a plurality of network interfaces, the packets also including trailers, and ii) respective trailer information extracted from the trailers of the packets. A packet processor is configured to process the header information and the trailer information in the packet descriptors to determine actions to be performed on the packets, including determining network interfaces via which at least some packets are to be transmitted by the network device. A transmit processor is configured to transmit the at least some packets via the plurality of network interfaces in accordance with the determining of network interfaces by the packet processor.

Network device configured to process packets with trailers

A network device is capable of transmitting and/or receiving packets that are encrypted according to a particular network security protocol, while being encapsulated according to any of a variety of tunneling protocols independent of the particular network security protocol. In such embodiments, a customer or network administrator can use the particular network security protocol while having the freedom to choose a particular tunneling protocol that is best suited for a network implementation instead of being limited to a specific tunneling protocol for a particular network security protocol.

Tunneling of MACsec frames

A packet processor of a network device receives packets ingressing from a plurality of network links via a plurality of network ports of the network device. The packet processor buffers the packets in an internal packet memory in a plurality of queues, including a first queue. In response to the packet processor detecting congestion in the internal packet memory, the packet processor selectively forwards a group of multiple packets in the first queue from the internal packet memory to a first port, among one or more ports coupled to one or more external memories, to transfer the group of multiple packets to a first external memory that is coupled to the first port so that the first queue is stored across the internal packet memory and the first external packet memory.

Packet buffer spill-over in network devices

Packets to be transmitted from a network device are buffered in queues in a first packet memory. In response to detecting congestion in a queue in the first packet memory, groups of multiple packets are transferred from the first packet memory to a second packet memory, the second packet memory configured to buffer a portion of traffic bandwidth supported by the network device. Prior to transmission of the packets among the one or more groups of multiple packets from the network device, packets among the one or more groups of multiple packets are transferred from the second packet memory back to the first packet memory. The packets transferred from the second packet memory back to the first packet memory are retrieved from the first packet memory and are forwarded to one or more network ports for transmission of the packets from the network device.

A signal processing device comprising at least one control unit arranged to receive at least one pack-insert instruction, decode the received at least one pack-insert instruction, and output at least one pack-insert control signal in accordance with the received pack-insert instruction. The signal processing device further comprising at least one pack-insert component arranged to receive at least a first data block to be inserted into a sequence of data blocks to be output to at least one destination register, receive a plurality of further data blocks to be packed within the sequence of data blocks to be output to the at least one destination register, arrange the at least first data block and the plurality of further data blocks into a sequence of data blocks based at least partly on the at least one pack-insert control signal, and output the sequence of data blocks.

Signal processing device and method of performing a pack-insert operation

A packet processing system and method for processing data units are provided. A packet processing system includes a processor, first memory having a first latency, and second memory having a second latency that is higher than the first latency. A first portion of a queue for queuing data units utilized by the processor is disposed in the first memory, and a second portion of the queue is disposed in the second memory. A queue manager is configured to push new data units to the second portion of the queue and generate an indication linking a new data unit to an earlier-received data unit in the queue. The queue manager is configured to transfer one or more queued data units from the second portion of the queue to the first portion of the queue prior to popping the queued data unit from the queue, and to update the indication.

Device and method for packet processing with memories having different latencies

A packet processing system comprises a plurality of packet processing nodes configured to process packets. The packet processing nodes are arranged in a plurality of packet processing clusters. The packet processing system also includes a plurality of prefetch buffers respectively associated with different ones of the packet processing clusters. A first prefetch buffer of the plurality of prefetch buffers is associated with a first packet processing cluster and is configured to store packets distributed for processing to the first packet processing cluster when the first packet processing clusters does not include any packet processing nodes available for processing of the packets.

Packet distribution with prefetch in a parallel processing network device

Embodiments include a network device comprising: at least one processing core; a packet processing module configured to perform a first set of packet processing operations at a first rate, to partially process data units that are received at the network device, the packet processing module being further configured to transmit ones of the data units to the at least one processing core, the at least one processing core being configured to perform a second set of processing operations at a second rate, wherein the second set of processing operations is different from the first set of processing operations; an interconnecting module configured to interconnect the packet processing module and the at least one processing core; and a rate limiter configured to selectively control a transmission rate at which the data units are transmitted by the packet processing module to the at least one processing core based on the second rate.

Method and apparatus for controlling a rate of transmitting data units to a processing core

Aspects of the disclosure provide a method for semiconductor wafer manufacturing. The method includes utilizing a subset of lower level masks in a mask set to form multiple modular units of lower level circuit structures on a semiconductor wafer. The mask set includes the subset of lower level masks and at least a first subset of upper level masks and a second subset of upper level masks. The first subset of upper level masks defines intra-unit interconnections. The second subset of upper level masks defines both intra-unit interconnections and inter-unit interconnections. The method further includes selecting one of at least the first subset of upper level masks and the second subset of upper level masks based on a composition request of a final integrated circuit (IC) product and utilizing the selected subset of upper level masks to form upper level structures on the semiconductor wafer.

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Hagor, Israel

Itay Peled