Microsoft Technology Licensing, LLC

Freescale Semiconductor,inc.

Itay Keidar

Benjamin Imanilov

Moshe Anschel

Itay S Peled

Ziv Zamsky

Yakov Tokar

Doron Schupper

Jonathan Golan

An electronic device has a sensor panel and a display upon which content is rendered in use. A control module controlling the sensor panel enters a whiteboard-style erase mode when specified conditions are met. The control module is configured to, in the whiteboard-style erase mode detect a first position on the sensor panel of a first point on a stylus; detect a second position on the sensor panel of a second point on the stylus, the second point being spaced from the first point; compute the location of the longitudinal axis of the stylus on the sensor panel from at least the detected first and second positions; and trigger an update of the rendered content at a location on the display related to the location of the longitudinal axis of the stylus on the sensor panel.

Control module for stylus with whiteboard-style erasure

A stylus includes a housing extending over a length and including a first end opposite a second end, a circuit configured to generate a signal, a power source configured to power generation of the signal, a writing tip extending from the first end of the housing, and a light harvesting unit configured to generate energy. The light harvesting unit includes a transparent window integral with the housing and positioned proximal to the writing tip, a panel of solar cells configured to absorb light received through the transparent window, optical fibers configured to transmit light from the window toward the panel of solar cells and an optical diffuser configured to diffuse the light transmitted by the optical fibers over a spatial extent of the panel of solar cells. The energy generated by the light harvesting unit is received by the circuit and configured to recharge the power source.

Stylus with light energy harvesting

A circuitry for a computing system comprising a first load/store unit, LSU, and a second LSU as well as a memory arrangement. The first LSU is connected to the memory arrangement via a first bus arrangement comprising a first write bus and a first read bus. The second LSU is connected to the memory arrangement via a second bus arrangement comprising a second write bus and a second read bus. The computing system is arranged to carry out a multiple load instruction to read data via the first read bus and the second read bus and/or to carry out a multiple store instruction to write data via the first write bus and the second write bus.

Circuitry for a computing system, LSU arrangement and memory arrangement as well as computing system

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Kfar Saba, Israel

Itay Keidar