Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Itaru Tamura

Osamu Takata

Naozumi Terada

Hiroyoshi Kitahara

Hidekazu Inoto

A semiconductor device includes a first semiconductor region of a first conductivity type, second, third and fourth semiconductor regions of a second conductivity type, a first insulating film, a second insulating film, a first electrode contacting the first insulating film, and a second electrode contacting the second insulating film. The second and third semiconductor regions contact the first semiconductor region. The fourth semiconductor region contacts the first semiconductor region, is disposed between the second semiconductor region and the third semiconductor region. The first insulating film contacts a first portion of the first semiconductor region between the second semiconductor region and the fourth semiconductor region. The second insulating film contacts a second portion of the first semiconductor region between the third semiconductor region and the fourth semiconductor region. The second insulating film is thicker than the first insulating film.

Semiconductor device

First wirings are disposed along a straight line in one row or one column of memory cell arrays. A second wiring is disposed above the first wirings and transmits a signal from one end of the second wiring to the other end thereof. Contact plugs connect the first wirings and the second wiring to each other. The first wirings are connected to a plurality of successive memory cells among all the memory cells in the row or column to which the first wirings belong. In case such an LSI is manufactured and defect analysis is made to thereby form an FBM, it is decided that the contact plugs connecting the first wirings to the second wiring are disconnected when a plurality of successive memory cells in one row or one column. Thus, a plurality of defects are expressed by the use of different categories.

Semiconductor device and LSI defect analyzing method using the same

A failure analyzing method using a failure-analyzing semiconductor device includes a first step of manufacturing a semiconductor device adapted for product in predetermined numbers during a first interval and a second step of manufacturing a failure-analyzing semiconductor device in predetermined numbers every second interval during the first interval. The first step includes a step of forming memory cells in a first semiconductor substrate. The second step includes a step of forming memory cells in a second semiconductor substrate and a step of forming first and second digitated interconnections at the same level above the second semiconductor substrate, which are connected to the memory cells and arranged so that the fingers of each of the first and second interconnections are interleaved with those of the other with a predetermined space therebetween.

Growing community of inventors

Tokyo, Japan

Itaru Tamura