Hitachi, Ltd.

Other

Renesas Electronics Corporation

Renesas Technology Corp.

Itaru Nonomura

Takahiro Yamada

Kenichi Osada

Yoshihiko Hotta

Shinichi Hashimoto

Seiichi Saito

Akio Hayashi

Hiroyuki Hamasaki

Kazuaki Tanaka

Makoto Saen

Hirotaka Hara

Kazushige Hiroi

Yasuhiro Furukawa

Yuuji Kimura

Nobukazu Kondo

Takeo Tomokane

Kazuhiro Fujisaki

Yoshiaki Eguchi

Naoko Iwami

Kei Suzuki

Yasuhisa Shimazaki

Kouki Noguchi

Shinichi Kato

Yasushi Nagai

Isao Takita

Toru Owada

Shigenobu Komatsu

Shin-ichi Hashimoto

Tetsuya Kawahara

Shinichi Sawamura

Takao Shimada

In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.

Semiconductor device and data processor

To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption. In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.

A semiconductor device including a pair of stacked semiconductor ICs capable of communicating with each other by wireless. Each IC has: a transmitter circuit operable to send, by wireless, transmit data together with a clock signal deciding a transmission timing, and arranged so that the wireless transmission timing is adjustable; a receiver circuit operable to receive data in synchronization with a clock signal received by wireless, and arranged so that its wireless reception timing is adjustable; and a control circuit operable to perform timing adjustments of the transmitter and receiver circuits based on a result of authentication of data returned by the other IC in response to data transmitted through the transmitter circuit, and received by the receiver circuit. This arrangement for near field communication between stacked semiconductor ICs enables: reduction of the scale of a circuit for communication timing adjustment; and highly accurate adjustment of the communication timing.

Semiconductor device and semiconductor integrated circuit

To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption. Ina data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.

A semiconductor device where multiple chips of identical design can be stacked, and the spacer and interposer eliminated, to improve three-dimensional coupling information transmission capability. A first semiconductor circuit including a three-dimensional coupling circuit (three-dimensional coupling transmission terminal group and three-dimensional coupling receiver terminal group); and a second semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode (power supply via hole and ground via hole); and a third semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode are stacked on the package substrate.

Semiconductor device with offset stacked integrated circuits

An interconnect configuration technology of making an access from an IP mounted on a semiconductor chip to an IP mounted on another semiconductor chip by transmitting and receiving a packet transferred through an interconnect built in a semiconductor chip among the chips using the 3D coupling technology. The device according to the technology has an initiator for transmitting an access request, a target for receiving the access request and transmitting an access response, a router for relaying the access request and the access response, and a 3D coupling circuit (three-dimensional transceiver) for performing communication with the outside, wherein the 3D coupling circuit is disposed adjacent to the router.

Semiconductor integrated circuit and semiconductor device with the same

In an LSI system using an on-chip bus, when a transfer on the bus is delayed due to a fully loaded buffer in a destination module, a source module cannot proceed to the next processing. Such an unwanted situation is eliminated by a transferring buffer which is provided on a transfer path in an on-chip bus on the LSI for temporarily storing transfer data. With this transferring buffer, even if a buffer within a slave module, specified as the destination, is fully loaded and cannot accept any more transfer, a bus master can transfer data to the transferring buffer provided on the on-chip bus. Thus, the bus master is not kept waiting for execution of a transfer, irrespective of the state of the buffer within the slave, thereby improving the processing performance of the entire system.

Integrated circuit and information processing device

A video data display board, device or method for inputting and displaying video data including vertical blanking interval data containing character data and other image data than the vertical blanking interval data. The video data display device has a data transfer circuit capable of transferring both of the data to devices different from each other, so that the processing of character information and image data are performed by using the different devices which perform an appropriate process according to the property of the data. The processed character and image data are displayed on a graphic display screen simultaneously.

Video data processing device and video data display device

A system which serves both as a host and a device cannot be realized with a single connector due to the constitution of hardware in the prior art. The prior art system only detects the existence of a device and cannot distinguish between a host and a device while a power source is turned on and switch its function. The information processing apparatus of the present invention separates the data lines of a host communication controller and the data lines of a device communication controller and activates the selected controller by means of selecting the data lines of the controllers and means of determining which is connected to a connector, a host or a device.

Information processing apparatus

A video data processing device which includes a bus, a central processing unit (CPU), a first scaling unit which is coupled to the bus and has an input unit for inputting image data from an external device, and a second scaling unit which is coupled to the bus. The CPU selectively controls the first scaling unit to convert the image data when an amount of the image data is decreased by a conversion performed by the first scaling unit, and selectively controls the second scaling unit to convert the image data when an amount of the image data is increased by the conversion performed by the first scaling unit.

Video data processing device and video data display device having a CPU which selectively controls each of first and second scaling units

Video data processing system

An information processing apparatus for processing video data and video data with audio data includes a scene change detecting device for particularly detecting a scene change of video data. The video data scene change detecting device includes an intra-coded frame detecting device for detecting a scene change between an intra-coded frame contained in video data and an intra-coded frame preceding the frame and a scene change information recording device for recording scene change information detected by the intra-coded frame detecting device.

Method of and an apparatus for decoding video data

In a data transfer system, a transmission terminal is provided with a transmission unit and a divisional transmission unit. A server station is provided with mailboxes, a transmission/reception management unit, a divisional reception unit and a divisional transmission unit. A reception terminal is provided with a reception,/reconstruction unit and a divisional reception unit. In the transmission of video mail from the transmission unit (or from the transmission/reception management unit) to the transmission/reception management unit (or to the reception/reconstruction unit), audio and a frame (still picture) representative of a motion picture, among data contained in the video mail, are first sent by an ordinary method. Video data in the video mail are thereafter transmitted from the divisional transmission unit to the divisional reception unit by a plurality of separate operations. Such a construction can realize data transfer of the video mail which relieves traffic in multimedia data transmission and also copes with the urgency of the mail while making the best use of an existing network.

Video mail system capable of transferring large quantities of data

According to a data amount reducing device for reducing the data amount of compressed video data in which the compressed video data has a format having a control information portion comprising control information which contains information on picture size and bit rate and is adapted to determine the characteristics of the compressed video data, and a data portion comprising compressed video data of plural frames, the data amount of intra-coded frames contained in the data portion in the compressed video data is reduced, and the control information is altered so as to match the compressed video data after the reduction processing.

Compressed video data amount reducing device, compressed video data

An image coding system and method thereof previously defines a plurality of combinations into a table. The table includes candidate values for quantizing steps and candidate values for upper limit values of space frequencies in correspondence with an image code size. The frequencies are coded into the pattern table on the basis of an error between the required code size, which is decided by the system performance, and required images. The generated code size is taken at the time of prediction coding between motion compensation frames. One combination of a quantizing step and upper limit values of space frequency are selected. The combination is coded from the candidate values depending on the image attribute and codes conforming to an international standard. The combinations are generated at a satisfactory coding efficiency. The coding efficiency is achieved by controlling the coding parameters depending on the image attribute and generated code size.

Growing community of inventors

Tokyo, Japan

Itaru Nonomura