Tokyo Electron Limited

Tokyo Electron Yamanashi Limited

Itaru Iida

Shinji Iino

Ken Nakao

Kiyoshi Takekoshi

Muneo Harada

Eiji Yamaguchi

Provided is a method for manufacturing a semiconductor device which includes: providing a plurality of semiconductor substrates formed with through holes which penetrate between main surfaces of the substrates and are filled with porous conductors; stacking the plurality of semiconductor substrates while aligning the porous conductors filled in the through holes; introducing conductive ink containing particle-like conductors into the porous conductors of the plurality of stacked semiconductor substrates; and sintering the plurality of stacked semiconductor substrates.

Method for manufacturing semiconductor device

A power supply applies a power supply voltage to a large number of devices formed on a wafer W. In the state where the devices are quiescent, the quiescent power supply currents flowing through them are measured. If measurements are greater than a setting value, the corresponding devices are determined to be defective. A cutoff circuit prevents voltage application to such defective devices. After this preliminary test, an IDDQ test, an AC test, a DC test and a function test are executed. These tests are executed not by a control station but by an application/measurement module provided for a prober.

Screening method of semiconductor device and apparatus thereof

A test system of the present invention is suitable especially for a reliability test. A reader (,) for reading a wafer identification code attached to a wafer (W) and a reader (,) for reading a shell identification code (,) attached to a test shell (,), are provided for an aligner (,). A reader (,) for reading the shell identification code (,) is provided for a rest apparatus. A transmission system (,) is provided, through which information read by the readers (,) are exchanged between the aligner (,) and the test apparatus (,). A storage devices (,) are used for storing the information. Owing to the use of these structural elements, the IC chips formed on a semiconductor wafer can be accurately tested with high efficiency. The test shell used in the test can be disassembled accurately and reliably.

System for testing semiconductor device formed on semiconductor wafer

A probe apparatus incorporated into a lighting inspection system for LCD panels, includes a store section, a process section, and a transfer section interposed between them. An examination mechanism having a probe card is arranged in an examination area of the process section. Right and left alignment areas are formed so as to interpose the examination area, and right and left work tables on which the LCD panels are to be loaded, are arranged on the right and left alignment areas, respectively. The movement of the right and left work tables is controlled by a controller, and the LCD panels on the right and left work tables are alternately examined in the examination area by the examination mechanism.

Apparatus for examining target objects such as LCD panels

A probe apparatus having a burn-in test function includes an apparatus body, a probe card, having a plurality of probes, for causing the plurality of probes to electrically contact a semiconductor wafer, a tester for measuring the electrical characteristics of the semiconductor wafer, heating and cooling mechanisms for applying a thermal stress to test target chips, as targets of the burn-in test, of the semiconductor wafer, and an electrical mechanism for applying an electrical stress to the chips.

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Nirasaki, Japan

Itaru Iida