Intel Corporation

Itamar S Kazachinsky

Tsvika Kurts

Jason W Brandt

Beeman C Strong

Ofer Levy

Zeev Sperber

Eliezer Weissmann

Alon Naveh

Michael Mishaeli

Doron Orenstein

Michael W Chynoweth

Rajshree Chabukswar

Peter Lachner

Gabi Malka

Simcha Gochman

Iris Sorani

Michael Kagan

Richard B O'Connor

Anthony Wojciechowski

Avner Lottem

Vikas R Vasisht

Yair Kazarinov

Matthew C Merten

Zeev Offen

Frank Binns

Stephen J Robinson

Peggy J Irelan

Mayank Bomb

Tal Gat

Md Asifur Rahman

A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.

Processor core power event tracing

A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.

Real time instruction trace processors, methods, and systems

In accordance with embodiments disclosed herein, there is provided systems and methods for providing status of a processing device with a periodic synchronization point in an instruction tracing system. For example, the method may include generating a boundary packet based on a unique byte pattern in a packet log. The boundary packet provides a starting point for packet decode. The method may also include generating a plurality of state packets based on status information of the processor. The plurality of state packets follows the boundary packet when outputted into the packet log.

Providing status of a processing device with periodic synchronization point in instruction tracing system

A method is described that involves referring to first information from a directory table in system memory. The first information includes location information and size information of a first slice of system memory where first tracing data is to be stored. The method also includes tracking the amount of tracing data stored in the first slice of system memory and comparing the amount against the size information. The method also includes, before the first slice of system memory is filled, referring to second information from the directory table in system memory, where, the second information includes location information and size information of a second slice of system memory where second tracing data is to be stored. The first slice is not contiguous with the second slice of system memory.

Processor that records tracing data in non contiguous system memory slices

Embodiments of the present invention provide an apparatus, system, and method of generating an execution instruction. Some demonstrative embodiments my include generating an execution instruction of a predetermined executable format based on memory address data of a memory-access instruction representing a memory address. Other embodiments are described and claimed.

Device, system and method of generating an execution instruction based on a memory-access instruction

A clock frequency control unit for an integrated circuit (IC) includes a clock generator, a finite state machine (FSM), and a gating circuit (GC). The FSM has at least first and second states corresponding to non-low workload low workload states, respectively. In the first state, the GC provides a clock signal to functional units of the IC with the same frequency as the clock generator output. In the second state, the GC reduces the frequency of the clock signal. In one embodiment, the GC masks out selected cycles of the clock generator output to reduce the clock signal frequency. The FSM monitors the operation of the IC to transition from the first state to the second state when selected 'low workload' conditions are detected (e.g., long latency cache miss). Similarly, the FSM transitions from the second state to the first state when selected 'non-low workload' conditions are detected.

Method and apparatus for reducing clock frequency during low workload periods

According to one embodiment, a computer system includes a memory and a central processing unit (graphics accelerator) coupled to the memory. The graphics accelerator is adaptable to process three-dimensional (3D) graphics primitives stored in the memory according to an inline streaming mode and an indirect streaming mode.

Method and apparatus for pre-fetching vertex buffers in a computer system

An improvement in a microprocessor having a cache memory providing strong and weak write ordering modes. The microprocessor includes a terminal for receiving a signal indicating whether an external write buffer is empty and an internal signal indicating whether an internal write buffer is empty. Operation of the microprocessor is halted in the strong ordering mode if the write buffers are not empty and a hit condition occurs during a write cycle until the buffers are empty.

Write ordering for microprocessor depending on cache hit and write

An improvement in a microprocessor permitting the selection of write-back, write-through or write-once protocols is disclosed. A pin is connected to either ground or Vcc potential to select either the write-through or write-back protocols. When this pin is connected to the read/write line, the write-once protocol is selected. Interconnection between two processors is described which permits the processors to operate in a write-once protocol with a minimum of glue logic.

Processor for multiple cache coherent protocols

Growing community of inventors

Natanya, Israel

Itamar S Kazachinsky