Intel Corporation

Itamar Levin

Eliezer Tamir

Ben-Zion Friedman

Adee Ofir Ran

Ariel Cohen

Ajay Balankutty

Tali Warshavsky

Shiva Kiran

Yekutiel Uliel

Marco Cusmai

Tali Warshavsky Grafi

Sampling circuitry for receiving an analog signal from photodetector circuitry and generating a sample analog signal. Equalization circuitry for generating an equalized signal comprising first and second sample values corresponding with a cursor tap and a first postcursor tap, and one or more third sample values corresponding with taps other than the cursor tap and the first postcursor tap. In the equalized signal, amplitudes of the first and second sample values are substantially equal while the third sample values are attenuated relative to the first and second sample values. The first and second sample values correspond with two or more first symbols of a first alphabet. Data slicer and modulo circuitry to generate a data signal based on the equalized signal and perform a modulo operation on the two or more first symbols and to generate one or more second symbols. The second symbols are according to a second alphabet.

Scalable receiver architecture for silicon photonic links

A CTLE-based SERDES receiver circuit using ISI metering provides an improved SERDES I/O performance. The CTLE SERDES receiver circuit may include an analog receiver frontend to generate an analog-to-digital converter (ADC) digital signal and a reduced ISI signal, a data path circuit to generate a sliced data stream and sliced cursor error stream, a digital signal processing (DSP) circuit to generate a converged data stream, a multi-tap intersymbol interference (ISI) assessment circuit to generate a weighted ISI sum, and an ISI minimization circuit to generate a continuous time linear equalizer (CTLE) adaptation control signal based on the weighted ISI sum.

Serdes circuit CTLE adaptation using ISI metering

An apparatus comprising at least one medium to transport a signal and an analog equalization circuit to perform equalization on the signal, wherein the analog equalization circuit comprises independently tunable parameters including a peak frequency gain and a mid-range frequency response slope.

Analog equalization with peaking and slope control

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Holon, Israel

Itamar Levin