Motorola Corporation

Ford Motor Company Limited

Optix Networks Inc.

Itai Katz

Ilan Pardo

Moti Kurnick

Avi Hagai

Vladislav Kopzon

Eran Kirzner

Edward Clark Nelson

David Shamir

Arye Peyser

Danny Shterman

Yaron Bar

Yuval Lachman

Noam Halevi

Oran Uzrad

Doron Shoham

Mark E Cummins

An apparatus and a method for accelerating Cyclic Redundancy Check (CRC) calculations. The apparatus includes a CRC circuit and an accelerator for accelerating the computation of the CRC code so that the CRC code is outputted immediately after the last bit of the input data stream is inserted to the CRC machine, thereby reducing the time required to compute the CRC calculation. The apparatus accelerates the CRC calculation by eliminating the need to append zeros to the input data stream.

Apparatus and method for accelerating cyclic redundancy check calculations

A reassembly unit comprising of a reassembly buffer and a control unit and a detector. The reassembly unit monitors an amount of data AMD stored in the reassembly register and compares AMD to four thresholds, TS1, TS2, TS3 and TS4. TS1 and TS4 define the size of the reassembly buffer. TS2 defines the delay of reassembly unit 40. A difference between TS1 and TS2 defines an underflow recovery period in which data is not read out of the buffer. A difference between TS4 and TS3 define an overflow recovery period in which data is not written in the buffer. The four thresholds can be changed during an operation of the reassembly unit, allowing a user to adjust the thresholds according to the state of the reassembly unit.

Reassembly unit and a method thereof

A multi-master bus system (,) comprises bus (,), a plurality of bus devices (,), coupled to the bus, including masters (,), and slaves (,), a memory controller (,) for controlling the data exchange on bus (,), having a memory (,) for storing a transaction type value with respect to each slave (,). The multi-master bus system (,) comprises further an arbiter (,) for performing bus arbitration, arbiter (,) having logic for conditionally subsequently granting the bus (,) to a master of an initiating transaction for a closing transaction depending on the transaction type value of the slave of the initiating transaction. The multi-master bus system makes atomic or indivisible transactions possible on a bus without changing the bus width or the bus protocol.

Multi-master bus system performing atomic transactions and method of operating same

An apparatus and method for implementing watchpoints and breakpoints in a data processing system (110). In one embodiment, a pipelined processor (110) performs each instruction of a program. One or more watchpoints are associated with the instructions. The processor includes a history buffer (50) for storing processor state values at the time when each of the instructions was executed, until a predetermined time. Watchpoint information associated with a particular watchpoint is also stored in the history buffer (50), in association with the processor state values, such that the processor state is changed and the watchpoint is announced at the predetermined time. The watchpoint information may include increment/decrement information for one or more counters (41, 42). Breakpoint information may also be stored in history buffer (50).

Apparatus and method for implementing watchpoints and breakpoints in a

A history buffer system (12) for allowing the recovery of executed instructions comprises main history buffer (14) for storing addresses of issued instructions and at least one subsidiary history buffer (16, 22) associated with a predetermined type of data, such as fixed or floating point data. The subsidiary history buffer (16, 22) has a plurality of entries (Y, Z), each entry for storing a pointer to a register (18, 26) and the data stored in the register. The main history buffer (14) is arranged to store control data (fxtag, fptag) which associates the entries in a subsidiary history buffer with the appropriate issued instructions of the same data type stored in the main history buffer. The main history buffer (14) may comprise a storage entry for each issued instruction, each storage entry having a field for storing the address of an issued instruction, and at least one tag field (fxtag, fptag) corresponding to the at least one subsidiary history buffer (16, 22) for storing the control data.

History buffer system

Growing community of inventors

Rehovot, Israel

Itai Katz