Sandisk Technologies Inc.

Sandisk Il Ltd.

Fortress U&t Ltd.

M-systems Flash Disk Pioneers, Ltd.

Ben-gurion University of the Negev Research and Development Authority

Fortress U&t Div. M-systems Flash Disk Pioneers Ltd.

Itai Dror

Carmi David Gressel

Isaac Hadad

Boris Dolgunov

Benjamin Arazi

Alon Kipnis

Michael Mostovoy

Itzhak Pomerantz

Rajeev Nagabhirava

Leonid Minz

Damian Pablo Yurzola

Ori Stern

Rahav Yairi

Arjun Kapoor

David Hendel

Alexey Molchanov

Jian Feng Chen

Yoav Weinberg

Meir Avraham

Xinmiao Zhang

Mark Fiterman

Roy Krotman

Norman S Kopeika

Robert Silvern

Peter Hwang

Carmi D Cressel

Michael Koun

Michael Fellner

Ofer Hadar

Annie Chi-San Chang

Alexander Berger

Michael Kun

Alexay Molchanov

Deny Hanan

Boris Dulgunov

Eddie Redmard

Eliyahu Fumbarov

Jian Chen

A method performed in a host device includes receiving an input based on a user-visible code associated with a data storage device. The user-visible code corresponds to an identifier of the data storage device. The method includes sending first data associated with the identifier to a server via a network and receiving, from the server at a first time, a copy of second data identifying content stored in the data storage device. The second data is stored in a network-based storage device associated with the server. The method includes displaying, via a user interface of the host device, an indication of the content of the data storage device to enable the content of the data storage device to be identified at the host device independently of whether the data storage device is coupled to the host device.

Systems and methods of storing data associated with content of a data storage device

A device includes a controller, and the controller includes a root detection circuit having multiple sets of multipliers. A method includes configuring the root detection circuit according to a degree of a polynomial. In response to detection of a root of multiple roots of the polynomial, a configuration of the root detection circuit is modified based on a polynomial degree reduction (PDR) scheme. Depending on the particular implementation, the device may be implemented in a data storage device, a communication system (e.g., a wireless communication device or a wired communication device), or another electronic device.

Low-power partial-parallel chien search architecture with polynomial degree reduction

A memory system comprising a non-volatile memory and a controller in communication with the non-volatile memory is disclosed. The controller may include a central processing unit ('CPU') and an internal cache in communication with the CPU via a plurality of cache lines. The CPU is configured to utilize a first subset of the plurality of cache lines when accessing data stored in the internal cache at a first resolution. Additionally, the CPU is configured to utilize a second subset of the plurality of cache lines when accessing data stored in the internal case at a second resolution, where the first and second resolutions are different resolutions.

Memory system controller including a multi-resolution internal cache

A method includes, in a data storage device, determining an estimated compression ratio. The estimated compression ratio is based on hash values of a subset of a data set. The method includes selectively processing the data set based on the estimated compression ratio prior to storage of data associated with the data set in a memory of the data storage device.

Method and apparatus to process data based upon estimated compressibility of the data

A memory device (e.g., a flash memory device) includes power efficient codeword error analysis circuitry. The circuitry analyzes codewords stored in the memory of the memory device to locate and correct errors in the codewords before the codewords are communicated to a host device that requests the codewords from the memory device. The circuitry includes a highly parallel configuration with reduced complexity (e.g., reduced gate count) that a controller may cause to perform the error analysis under most circumstances. The circuitry also includes an analysis section of greater complexity with a less parallel configuration that the controller may cause to perform the error analysis less frequently. Because the more complex analysis section runs less frequently, the error analysis circuitry may provide significant power consumption savings in comparison to prior designs for error analysis circuitry.

Parallelization of error analysis circuitry for reduced power consumption

A data storage device includes a memory and a controller. A method performed in the data storage device includes performing a first transformation of a unit of data to generate a first transformed unit of data. Performing the first transformation includes sorting permutations of the unit of data. The method includes performing a move-to-front transformation of the first transformed unit of data to generate a second transformed unit of data. The method includes performing a weight-based encoding of the second transformed unit of data to generate an encoded unit of data. The encoded unit of data has a same number of bits as the unit of data.

Encoding data for storage in a data storage device

Systems and methods for performing wear leveling are disclosed. In one implementation, a controller partitions a memory block into at least a first partition and a second partition. The controller utilizes the first partition of the memory block for storage of data blocks until the first partition reaches a first end of life condition. After the first partition reaches the first end of life condition, the controller utilizes the first partition for storage of data blocks associated with a compression ratio that is less than a compression threshold until the first portion reaches a second end of life condition. The controller additionally utilizes the second partition for the storage of data blocks until the second partition reaches the first end of life condition.

Systems and methods for performing variable flash wear leveling

A semiconductor device, such as a semiconductor die, is disclosed including embedded temperature sensors for scanning the junction temperature, Tj, at one or more locations of the semiconductor die while the die is operating. Once a temperature of a hot spot is detected that is above a temperature specified for the die or package containing the die, the die/package may be discarded. Alternatively, the functionality of the die may be altered in a way that reduces the temperature of the hot spots.

Tj temperature calibration, measurement and control of semiconductor devices

A method and memory device for generating a time estimate are provided. In one embodiment, a memory device generates a time estimate from time stamps in file system metadata for a plurality of files stored in the memory device and uses the time estimate to perform a time-based activity in the memory device. In another embodiment, a memory device generates a time estimate from time stamps stored in a plurality of files stored in the memory device and uses the time estimate to perform a time-based activity in the memory device. In yet another embodiment, a memory device obtains a plurality of time stamps, selects one or more of the plurality of time stamps based on validity rankings, generates a time estimate from the selected time stamp(s), and uses the time estimate to perform a time-based activity in the memory device.

Method and memory device for generating a time estimate

A system for random number generation includes a digital oscillator circuit, which has a set of available configurations and is operative to generate a random number sequence in accordance with a current configuration selected from the set. The system further includes a randomization circuit, which is operative to produce a pseudo-random stream of values corresponding to the available configurations of the digital oscillator circuit, and to control the digital oscillator circuit to alternate among the available configurations in accordance with the pseudo-random stream of values.

Digital random number generator based on digitally-controlled oscillators

A method includes initiating a compression operation to compress data to be stored in a group of storage elements at a memory device that includes an error correction coding (ECC) engine. The method includes selecting one of a first mode of the ECC engine to generate a first number of parity bits and a second mode of the ECC engine to generate a second number of parity bits based on an extent of compression of the data. The method also includes encoding the compressed data to generate parity bits corresponding to the compressed data and storing the compressed data and the parity bits to the group of storage elements according to a page format that includes a data portion and a parity portion. The compressed data is stored in the data portion and at least some of the parity bits are stored in the parity portion.

System and method of error correction of control data at a memory device

A controller coupled to a memory array includes an error correction coding (ECC) engine and an ECC enhancement compression module coupled to the ECC engine. The ECC enhancement compression module is configured to receive and compress control data to be provided to the ECC engine to be encoded. Compressed encoded control data generated at the ECC engine is stored as a codeword at the memory array.

A decoder is disclosed that can reduce power consumption at different stages of a decoding process. At a first stage where the decoder calculates residual values, the decoder can reduce power consumption by calculating residual values using less than a full set of division circuits. A reduced number of division circuits may be sufficient to successfully calculate residuals associated with the codeword to complete the decoding process. Division circuits that are not used may be disabled to reduce power consumption. At another stage of the decoding process where the decoder generates coefficients that are used to identify locations of errors in the codeword, the decoding process can limit power consumption by reducing the number of iterations of a polynomial generator by incorporating termination decision circuitry.

System and method of decoding data with reduced power consumption

A method for random number generation includes generating random number sequences using a Random Number 5 Generator (RNG) circuit having an externally-modifiable configuration. The RNG circuit generates a first random number sequence having a first measure of randomness, and modifies the configuration of the RNG circuit, causing the RNG circuit to generate a second random number sequence having a second measure of the randomness, indicating a degree of the randomness that is no less than the first measure.

Configurable random number generator

Growing community of inventors

Omer, Israel

Itai Dror