Amazon Technologies, Inc.

Itai Avron

Adi Habusha

Erez Sabbag

Ali Ghassan Saidi

Ofer Naaman

Tzachi Zidenberg

Benny Pollak

Gal Kochavi

Nafea Bshara

Guy Nakibly

Uri Leder

Dan Trock

Svetlana Kantorovych

Sergey Kleyman

Roi Ben Haim

Anna Rom-Saksonov

Simaan Bahouth

Yair Armoza

Yaakov Gendel

Danny Sapoznikov

Ariel Pescovsky

Maxim Tzipori

Gal Paikin

Valentin Bader

Shlomi Vilozny

Shimon Rahamim

An integrated circuit to synchronize a pulse signal from a first clock domain to a second clock domain includes a first flip-flop and a second flip-flop. The first flip-flop has a first stage input, a first clock input, and a first stage output. The first clock input is driven by a first clock signal of the first clock domain, and the first stage input is driven by a result of XOR-ing the input pulse signal and the first stage output. The second flip-flop has a second stage input, a second clock input, and a second stage output. The second clock input is driven by a second clock signal of the second clock domain, and the second stage input is driven by the first stage output. The synchronized output pulse signal is generated by XOR-ing the second stage output with the first stage output.

Low latency synchronization

A decoder is disclosed with error correction for memory data. The decoder's error correction is extended to additional faulty bits by integrating a memory test into the error correction to identify faulty bits in the memory data. A method for correction can include writing a known pattern to the failing address (and possibly to neighboring addresses), reading the known pattern back and comparing the read data to the written pattern to identify the failing bits. The failing bits are then used together with the error correction data to correct memory data having multiple incorrect bits or to alert other components about the failing bit locations.

Correcting memory data using an error code and a memory test result

Systems and methods are provided to improve a communication channel dynamically and autonomously based on the status of the communication traffic on the communication channel between a first integrated circuit (IC) and a second IC. The communication traffic on the communication channel can be monitored, and latency, bandwidth, link quality, or power consumption associated with the communication channel for the monitored communication traffic can be determined dynamically. A modified protocol for the communication channel that can improve the communication channel as compared to an existing protocol can be determined based on the information related to the latency, bandwidth, link quality, or the power consumption. The existing protocol can be changed autonomously to the modified protocol as the communication traffic varies.

Dynamic improvement of a communication channel

An interposer circuit is used between an interrupt controller and a processor core to facilitate direct injection of a virtual interrupt into a guest executing on the processor core, even though the interrupt controller does not support the direct injection. The interposer circuit can convert a command received from the interrupt controller for a physical interrupt into another command for a virtual interrupt to make the processor core believe that the processor core has received a virtual interrupt even though the interrupt controller is not able to provide the virtual interrupt. The virtual interrupt can be directly injected into the processor core without the intervention of a hypervisor executing on the processor core.

Direct injection of a virtual interrupt

Systems and methods are disclosed to provide an autonomous management of communication links between dice on a multi-die assembly. Each die can include a detection unit and a controller to detect a failing communication link and perform link maintenance by directing the communication traffic on the failing link to an operational link before the link fails. Once the failing link has been repaired, the controller can re-direct the traffic back to the repaired link. The controllers on each die can negotiate through a handshake process to provide the continuous operation by switching the communication traffic from the failing link to the operational link, and then from the operational link to the repaired link.

Autonomous management of communication links

Techniques for encoding additional data in a memory without requiring an increase to the physical storage capacity of the memory device are described. Additional data can be encoded with error correction code symbols without having to physically store the additional data in memory, while retaining the number of error correction code bits used by the memory. When data is read from memory without the additional data, erasure decoding can be performed to recover the additional data. When errors are encountered in the data read from memory, the errors can be treated as erasures for different predictions of the error locations to determine if the errors can be corrected.

Memory extension with error correction

Systems, apparatuses, and corresponding techniques are described for selective erasure decoding on memory devices. Erasure decoding is performed on error correction codes (ECCs) read from memory locations associated with errors that are correctable through erasure decoding, as indicated by erasure information available to a memory controller or other device configured to decode ECCs. The erasure information can indicate locations within individual memory devices and, optionally, at different memory hierarchy levels. When the erasure information indicates that a location being read from is not associated with an error that is correctable through erasure decoding, regular error decoding is performed on ECCs read from such locations. Selective erasure decoding can be performed in connection with separate read operations that access different memory devices or a single read operation that accesses multiple memory devices concurrently.

Selective erasure decoding for memory devices

A dedicated input/output (I/O) cache can be used for I/O-to-processor communications. Data received from an I/O device can be written to the I/O cache and also written to a device memory that is accessible to the processor. The processor can then access the data in the fast, dedicated I/O cache if available. Otherwise, the processor can read the data from the memory into a conventional processor cache for processing. Writes to the cache can be full or partial, with partial writes utilizing padding in some embodiments. The data can be written sequentially in a circular manner. Data processed by the processor can be invalidated, and invalidated data can be overwritten on a subsequent write. Phase bits can also be used to indicate the pass during which various writes were performed.

Dedicated communications cache

An integrated circuit includes first and second cores. Each core has a power-switchable portion in a first power domain in which an operating power is turned on or off in response to a power control signal. The first power domain includes a first scan chain, and the first power domain also includes a plurality of outputs. Each core also includes an always-on portion in a second power domain in which the operating power is maintained during testing of the integrated circuit. The second power domain also has a second scan chain. The second power domain further includes respective isolation gates coupled to the plurality of outputs of the first power domain, and the second scan chain includes a respective wrapper cell coupled to some isolation gates. The integrated circuit is configured to power off and isolate the power-switchable portion in the first power domain based on a scan test result.

Yield-oriented design-for-test in power-switchable cores

In a memory controller, a prefetch indication can be sent to memory to prepare the memory for a potential future read or write. Statistics can be used to select when such a prefetch should occur. The prefetch can occur without any read or write command being commenced. As a result, the memory controller predicts when to perform the prefetch. Some examples of when a prefetch can be sent include when there are other requests for the same memory page, or how often the page is requested. The page can remain open to prevent it from closing until the relevant read or write arrives. In the case that a read or write does not occur after a predetermined period of time, then a precharge can be performed to release the memory page.

Predictive prefetch of a memory page

A method and circuit are disclosed to calculate an error correction code (ECC) and perform a decompression in parallel when reading memory data. There are multiple modes of operation. In a normal parallel mode of operation, the data passes through a decompression engine. Simultaneously, the same data passes through an ECC decode engine. However, if no error is detected, the output of the decode engine is discarded. If there is an ECC error, an error indication is made so that the corresponding data exiting the decompression engine is discarded. The circuit then switches to a serial mode of operation, wherein the ECC decode engine corrects the data and resends the corrected data again through the decompression engine. The circuit is maintained in the serial mode until a decision is made to switch back to the parallel mode, such as when a pipeline of the ECC engine becomes empty.

Memory controller with parallel error checking and decompression

A method and circuit are disclosed to calculate an error correction code (ECC) and perform a decryption in parallel when reading memory data. There are multiple modes of operation. In a normal parallel mode of operation, the data passes through a decryption engine. Simultaneously, the same data passes through an ECC decode engine. However, if no error is detected, the output of the decode engine is discarded. If there is an ECC error, an error indication is made so that the corresponding data exiting the decryption engine is discarded. The circuit then switches to a serial mode of operation, wherein the ECC decode engine corrects the data and resends the corrected data again through the decryption engine. The circuit is maintained in the serial mode until a decision is made to switch back to the parallel mode, such as when a pipeline of the ECC engine becomes empty.

Memory controller with parallel error checking and decryption

Disclosed herein is a distributed performance monitor circuit that includes a plurality of performance monitors connected to a cross-trigger network. Each performance monitor corresponds to a respective functional block of a system and includes a counter circuit. The counter circuit includes a programmable time window counter configured to determine an adjustable counting period, and an event counter configured to count a number of occurrences of an event occurring in the respective functional block during the counting period. The cross-trigger network is configured to receive an output trigger signal generated by a performance monitor when the number of occurrences of the event occurring in the corresponding functional block during the counting period is outside of a threshold band for the performance monitor, and send an input trigger signal to the plurality of performance monitors based on receiving the output trigger signal.

Time-based on-chip hardware performance monitor

Provided are methods and adapter devices for buffering write transactions directed to a large space. In various implementations, an adapter device may include a sequential address buffer and a memory. A region of the memory may be configured as a data block, which may be associated with an address range. The address range may correspond to a region of an address space of a target device. The adapter device may be configured to receive a write transaction, the write transaction having an address and data. The adapter device may further write the address to the sequential address buffer. The adapter device may further determine that the address is within the address range, and to write the data to the data block. The adapter device may further, upon the occurrence of an event, write the data from the data block to the region of the address space of the target device.

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Petah Tikva, Israel

Itai Avron