Sun Microsystems, Inc.

Oracle America, Inc.

Istvan Novak

Michael C Freda

Larry D Smith

Valerie St Cyr

Shlomo D Novotny

David Hockanson

Leesa Noujeim

Merle Tetreault

Daniel D Gonsalves

Ali Hassanzadeh

Robert Moffett

Valerie StCyr

Eric L Blomberg

Deborah Foltz

Wai-Yeung Yip

Daniel C Irish

Kenneth Laird

Wigneswaran W Balasingham

Kenneth M Weiss

Jason R Miller

A stable power, low electromagnetic interference (EMI) apparatus and method for connecting electronic devices and circuit boards is disclosed. The apparatus involves a capacitor which includes a body member, a set of power terminals and a set of ground terminals connected to the top of the body member. The set of power terminals and the set of ground terminals alternate one with another. As a result of this configuration, a high inductance on the PCB side is achieved. The capacitor further includes a set of terminals connected to the bottom of the body member and includes metal planes within the body member. The metal planes are positioned to electrically connect either the set of power terminals or the set of ground terminals to the set of terminals.

Power integrity circuits with EMI benefits

An adaptive subgridding method for power/ground plane simulations. The method includes superimposing a grid of cells onto a circuit plane. For each cell, the method may determine a fill ratio representing the amount of area in a given cell that overlaps with the circuit plane. For each cell having a fill ratio that is less than a predetermined upper limit or a predetermined lower limit the cell may be divided into a plurality of subcells. The method may then determine the fill ratio for each of the subcells. As with the original cells, each of the subcells having a fill ratio less than the predetermined upper limit and greater than the predetermined lower limit may be further subdivided into additional subcells. The loop may repeat itself until a predetermined integer value is reached, wherein the integer value indicates the number of times a cell may be subdivided.

Method for adaptive sub-gridding for power/ground plane simulations

A bolster plate apparatus, used to secure a semiconductor device intermediate a printed circuit board and a heat sink apparatus, includes either an indentation or an open aperture into which a radio frequency absorptive material may be disposed. The absorptive material may be a ferrite material specifically selected to absorb frequencies in the range of the second to fourth harmonic of the processor clock signal frequency. The type of the ferrite material implanted in the bolster plate is selected to maximize the absorption of radio frequency energy, particularly that emitted at the pad vias on the underside of the printed circuit board, without affecting the signal integrity of the other pad connections. The shape of the cutout or aperture is also defined by the arrangement of RF emitting pads on the underside of the printed circuit board. The open aperture, without any absorptive material, effectively increases the distance between the source of the radio frequency energy and the metal body of the bolster plate, thereby reducing the amount of radio frequency energy absorbed by the bolster plate and the electromagnetic interference generated thereby. Also disclosed is a method for reducing the radiated emission from an adjacent semiconductor device by selectively removing pads from the undersurface of the PCB board to effectively reduce the sources of the radio frequency energy, and, therefore the amount of RF energy capacitively coupled with RF energy metal body of the bolster plate.

Method and apparatus for reducing capacitively coupled radio frequency energy between a semiconductor device and an adjacent metal structure

A system and method for distributing power to an integrated circuit. In one embodiment, a power laminate may be mounted to a printed circuit board (PCB). The integrated circuit for which power is to be distributed may be electrically coupled to the PCB. The power laminate may include one or more power planes and one or more reference (i.e. ground) planes, with each pair of power/reference planes separated by a dielectric layer. The power laminate may also include a connector or other means for receiving power from an external power source. The power laminate may be electrically coupled to the integrated circuit, thereby enabling it to provide power to the integrated circuit. The power laminate may also include a voltage regulator circuit, and a plurality of decoupling capacitors.

Power distribution system with a dedicated power structure and a high performance voltage regulator

A socket, such as a Land Grid Array (LGA) socket, for forming electrical connections between a first surface having a first contact array and a second surface having a second contact array. The socket includes a plurality of compliant contacts, each contact inserted into one of a plurality of passages that extend through a plate. Each contact has a first contact surface for electrically engaging the first contact array, and a second contact surface for electrically engaging the second contact array. At least one of the contacts is a low current contact, and at least one of the contacts is a high current contact capable of passing more current than the low current contact.

Land grid array socket with diverse contacts

An interconnecting apparatus employing a lossy power distribution network to reduce power plane resonances. In one embodiment, a printed circuit board includes a lossy power distribution network formed by a pair of parallel planar conductors separated by a dielectric layer.

Printed circuit board employing lossy power distribution network to reduce power plane resonances

A chip package for reduced EMI. In one embodiment, a chip package includes a semiconductor chip mounted on a substrate. First and second horizontal conductors may be present within the substrate. The semiconductor chip is coupled to the first and second horizontal conductors by a first and second pluralities of vertical conductors, respectively. The silicon chip may receive power via the first horizontal conductor and the first plurality of vertical conductors. The first and second horizontal conductors are connected to external connectors by third and fourth pluralities of vertical conductors, respectively. One or more capacitors may be electrically coupled between the first and second horizontal conductors.

Chip packaging and connection for reduced EMI

A method for constructing a capacitor having an increased equivalent series resistance (ESR) is disclosed. In one embodiment, a capacitor includes a plurality of capacitor plates comprised of a conductive material and first and second capacitor terminals. At least one of the capacitor plates is coupled to the first terminal and at least one of the capacitor plates is coupled to the second terminal. At least one of the plurality of capacitor plates includes a pattern, wherein the pattern is void of conductive material. The void in the conductive material formed by the pattern may cause a path of current flow through the capacitor plate to be substantially altered in comparison to a capacitor plate that is continuous. By using capacitor plates having voids of conductive material that cause the current path to be altered in comparison to continuous capacitor plates, a capacitor can be constructed having a higher ESR.

Capacitor having plates with a pattern void of conductive material and method of making therfor

A system and method for distributing power to an integrated circuit. In one embodiment, a power laminate may be mounted to a printed circuit board (PCB). The integrated circuit for which power is to be distributed may be electrically coupled to the PCB. The power laminate may include one or more power planes and one or more reference (i.e. ground) planes, with each pair of power/reference planes separated by a dielectric layer. The power laminate may also include a connector or other means for receiving power from an external power source. The power laminate may be electrically coupled to the integrated circuit, thereby enabling it to provide power to the integrated circuit. The PCB may include a signal layer for conveying signals to and from the integrated circuit, but does not include any means for providing core power to the integrated circuit. Thus, all core power provided to the integrated circuit may be supplied by the power laminate.

Method and apparatus for distributing power to integrated circuits

A method for achieving a desired value of electrical impedance between conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the conductors. The resistance elements may be annular resistors, and may provide the designer a greater degree of control of the system ESR. The annular resistors may comprise a first terminal, an annular resistor, and a second terminal. The second terminal may be located within the confines of the annular resistor. The annular resistors may be printed onto a conductive plane (e.g. a power plane or a ground plane), or may be a discrete component.

Adding electrical resistance in series with bypass capacitors using annular resistors

Several methods are presented for achieving a desired value of electrical impedance between parallel planar conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors between the planar conductors. The methods include bypass capacitor selection criteria based upon simulation results. An exemplary electrical power distribution structure produced by one of the methods includes a pair of parallel planar conductors separated by a dielectric layer, and n discrete electrical capacitors electrically coupled between the planar conductors, where n&gE;2. The n capacitors have substantially the same capacitance C, mounted resistance R , and mounted inductance L . The electrical power distribution structure achieves an electrical impedance Z at a mounted resonant frequency f of the capacitors. The mounted resistance R of each of the n capacitors is substantially equal to (n&middot;Z). The mounted inductance L of each of the n capacitors is less than or equal to (0.2&middot;n&middot;&mgr; &middot;h), where &mgr; is the permeability of free space, and h is a distance between the planar conductors. The mounted resistance R of each capacitor is the sum of an equivalent series resistance (ESR) of the capacitor and the electrical resistances of all conductors coupling the capacitor between the planar conductors. The mounted inductance L of each capacitor is the electrical inductance resulting from the coupling of the capacitor between the planar conductors. The mounted resonant frequency &fnof; results from capacitance C and mounted inductance L .

BYPASS CAPACITOR METHODS FOR ACHIEVING A DESIRED VALUE OF ELECTRICAL IMPEDANCE BETWEEN PARALLEL PLANAR CONDUCTORS OF AN ELECTRICAL POWER DISTRIBUTION STRUCTURE, AND ASSOCIATED ELECTRICAL POWER DISTRIBUTION STRUCTURES

Apparatus and methods for achieving a desired value of electrical impedance between parallel planar conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the planar conductors. The methods include bypass capacitor selection criteria and electrical resistance determination criteria based upon simulation results. An exemplary electrical power distribution structure produced by one of the methods includes a pair of parallel planar conductors separated by a dielectric layer, n discrete electrical capacitors, and n electrical resistance elements, where n&gE;2. Each of the n discrete electrical resistance elements is coupled in series with a corresponding one of the n discrete electrical capacitors between the planar conductors. The n capacitors have substantially the same capacitance C, mounted resistance R , mounted inductance L , and mounted resonant frequency f . The mounted resistance R of each of the n capacitors includes an electrical resistance of the corresponding electrical resistance element. The electrical power distribution structure achieves an electrical impedance Z at the resonant frequency f of the capacitors. The mounted resistance R of each of the n capacitors is substantially equal to (n&middot;Z). The mounted inductance L of each of discrete electrical capacitors, and n electrical resistance elements, where n&gE;2. Each of the n capacitors is less than or equal to (0.2&middot;n&middot;&mgr; &middot;h), where &mgr; is the permeability of free space, and h is a distance between the planar conductors.

Adding electrical resistance in series with bypass capacitors to achieve a desired value of electrical impedance between conductors of an electrical power distribution structure

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Maynard, MA, United States of America

Istvan Novak