Tower Semiconductor Ltd.

Saifun Semiconductors Ltd.

Israel Rotstein

Boaz Eitan

Yossi Netzer

Ephie Koltin

A fieldless CMOS image sensor that include a non-LOCOS isolation structure surrounding the photodiode diffusion region of each pixel. The isolation structure is formed by an anti-punchthrough (APT) implant isolation region formed in the substrate around the photodiode diffusion region, and spacer oxide that is formed using a special mask to cover the APT implant region. The APT implant isolation region is self-aligned with the special spacer oxide mask. A width of the isolation structure between two adjacent photodiodes is 0.5 &mgr;m or more. Similarly, LOCOS structures that are used, for example, in the image sensor active circuitry, are separated from the image-sensing (e.g., photodiode) region of each pixel by portions of the isolation structure having a width of 0.5 &mgr;m or more.

Fieldless CMOS image sensor

A method for forming a CMOS image sensor cell such that stress is minimized in regions surrounding the light sensitive (e.g., photodiode) portion of the cell, thereby reducing leakage current and minimizing white spots in CMOS image sensors. The field oxide surrounding the light sensitive region is formed with interior angles greater than 90&deg; and/or is continuously curved. The reset gate is offset from the light sensitive regions of active pixel cells by a distance greater than 0.25 &mgr;m. A mask is used during n&plus; doping of the light sensitive region to shield an inner edge of the surrounding field oxide and extends 0.5 &mgr;m or more over the light sensitive region. A mask is provided over the interface between the field oxide and the light sensitive region during sidewall spacer formation. A metal structure contacting the light sensitive region is spaced 0.4 &mgr;m or greater from the surrounding field oxide. Metal lines passing between the light sensitive regions are provided with stress-relieving slits. Metal lines of a guard ring surrounding the pixel array are non-continuous to also provide stress relief.

Method and structure for minimizing white spots in CMOS image sensors

A method for manufacturing a memory array having a plurality of memory cells thereon and diffusion areas therebetween includes the steps of laying down a layer of silicon nitride, defining the diffusion areas and creating diffusion oxides over the diffusion areas. Both steps of laying down and defining occur without etching any part of the layer of silicon nitride. The step of creating diffusion oxides includes the steps of creating porous silicon nitride from portions of the silicon nitride layer wherever diffusion oxides are desired (typically by laying down photoresist in a desired pattern and bombarding the silicon nitride layer with ions) and oxidizing both the porous silicon nitride and the silicon substrate through the porous silicon nitride thereby to create silicon oxy-nitride and silicon dioxide, respectively. The present invention also includes a semiconductor chip having diffusion or bit line oxides formed of at least silicon oxy-nitride.

Growing community of inventors

Migdal Haemek, Israel

Israel Rotstein