Motorola Corporation

Other

Solavolt International

Israel A Lesk

George W Hawkins

Michael G Coleman

Ronald E Thomas

Francine Y Robb

Robert A Pryor

Lowell E Clark

Michael C Keeling

William L Bailey

Kalluri R Sarma

Curtis D Moyer

Ronald N Legge

Richard W Gurtler

Lewis E Terry

Hang M Liaw

Schyi-Yi Wu

Steven A Voight

Frank S d'Aragona

Hassan Pirastehfar

Bich-Yen Nguyen

Robert Bruce Davies

Michael B McShane

Philip J Tobin

Paul T Lin

Peter J Zdebel

James J Casto

Raymond C Wells

Robert E Rutter

Clarence A Lund

Jonathan C Dahm

M John Rice, Jr

Ralph J Ellis

John G Franka

Young Limb

Steven J Adler

James M Rugg

Han-Bin K Liang

William L Hunter

Gary L Huffman

Frank T Secco d'Aragona

Peter L Pegler

Robert Maxwell Handy

Cynthia B Harris

Thomas C Smith

A method useful in the backside processing of semiconductor wafers includes providing a semiconductor wafer having a first surface that has been substantially processed. The processed first surface of the semiconductor wafer is bonded to a handle wafer. Once bonded to the handle wafer, backside processing may be performed on the wafer. Following backside processing, the wafer is sawn while still bonded to the handle wafer. The individual dice are then removed from the handle wafer. This process involves fewer handling steps of the semiconductor wafer and the handle wafer provides support to the semiconductor wafer during backside processing thereby reducing opportunities for breakage.

Backside processing method

A method for making a semiconductor structure which may be subject to small particle contaminants (12) includes pre-reacting the small particle (12) with a substrate (10) at a reaction temperature (27, 28). Pre-reacting the particle's (12) greatly reduces the particles' susceptibility to further reaction during subsequent processing, particularly gate dielectric formation. Consequently, the pre-reacted particle (13) as well as the remainder of the structure surface (11) can be covered with a high quality conformal deposited dielectric (14) which maintains a uniform thickness. Potential localized high leakage current density regions are thereby reduced. Additionally, an undesirably thin gate oxide region (70) adjacent a thick field oxide region (66) of a typical MOS structure is eliminated. Yield and reliability are thereby enhanced.

Semiconductor structure with stable pre-reacted particle and method for

A plurality of doped areas (12, 13, 14) are formed on a surface of a semiconductor wafer. A titanium nitride layer (17) is used for covering the plurality of doped areas (12, 13, 14) and for providing electrical connection between the doped areas (12, 13, 14). The titanium nitride layer (17) substantially prevents dopants from diffusing into the titanium nitride (17) and subsequently counterdoping the doped areas (12, 13, 14) during subsequent high temperature processing operations.

Method of forming a conductive diffusion barrier

A method for gettering metallic impurities from a semiconductor substrate (25). A gettering structure is fabricated in inactive areas of a semiconductor chip (31). The gettering structure is manufactured by forming an oxide (30) having a bird's head structure contacting a heavily doped region (28). The combination creates precipitation nuclei to which the metallic impurities migrate. The metallic impurities are sequestered by the precipitation nuclei or trap sites and rendered incapable of degrading the electrical characteristics of a semiconductor device.

Method of making a structure for top surface gettering of metallic

Reactor atoms (22) are introduced into a silicon substrate (10) by ion implantation to combine with metal impurities (18) to form stable chemical compounds (24). The stable compounds do not decompose and release the metal impurities during subsequent processing steps. Such metal impurities are detrimental to semiconductor devices formed in active regions (16, 17) in the silicon substrate. The reactor atoms such as sulfur are chosen to be substantially immobile in silicon at normal semiconductor processing temperatures. The metal impurities such as iron are effectively gettered to increase performance and reliability of semiconductor devices formed in the active regions (16, 17) in the silicon substrate.

Gettering of impurities by forming a stable chemical compound

A field plate avalanche diode has a field plate extending over the breakdown PN junction.

Field plate avalanche diode

An ohmic contact to a III-V semiconductor material is fabricated. First, a III-V semiconductor material is provided. Source/drain regions are then formed in the III-V semiconductor material. On the III-V semiconductor material, a contact system is formed which is dry etchable using reactive ions such as chlorine or fluorine and substantially free of arsenic. Subsequently, a portion of the contact system is dry etched using reactive ions such as chlorine or fluorine to leave a portion of the contact system remaining on the source/drain regions. Then, the III-V semiconductor material and the contact system are annealed in an atmosphere substantially free of arsenic at a temperature at which at least a part of the contact system is alloyed with the source/drain regions to form an ohmic contact with the source/drain regions of the III-V semiconductor material.

Ohmic contact for III-V semiconductor materials

A method substantially eliminating consumption of silicon from semiconductor devices is provided. The method includes controlling gases within the environment wherein the semiconductor device is positioned. The environment is formed to include an inert gas and oxygen. The oxygen content is formed to have a concentration between approximately 1.times.10.sup.1 and 1.times.10.sup.5 parts per million. Such an oxygen concentration substantially prevents converting silicon from the semiconductor device into silicon monoxide thereby substantially eliminating silicon consumption.

Method of processing a polycide structure

A plurality of doped areas (12, 13, 14) are formed on a surface of a semiconductor wafer. A titanium nitride layer (17) is used for covering the plurality of doped areas (12, 13, 14) and for providing electrical connection between the doped areas (12, 13, 14). The titanium nitride layer (17) substantially prevents dopants from diffusing into the titanium nitride ( 17 ) and subsequently counterdoping the doped areas (12, 13, 14) during subsequent high temperature processing operations.

Conductive diffusion barrier of titanium nitride in ohmic contact with a

Contaminants are removed from a semiconductor material by heating the semiconductor material to temperature within the range of a minimum temperature where a halogen compound will decompose to halogen atoms without the use of ultraviolet irradiation and react with contaminants present on the semiconductor material and a maximum temperature of 800.degree. C., wherein less than or equal to approximately 50 Angstroms of oxide is formed on the semiconductor material. The ambient in which the semiconductor material is heated is an ambient comprised of a nonreactive gas and a halogen compound for at least a time sufficient to remove a substantial amount of contaminants from the semiconductor material.

Method of removing contaminants

Method of forming an ohmic contact to III-V semiconductor materials

A dielectric and conductive isolated island is fabricated by providing an active wafer having a first and a second major surface, a doped region extending from the first surface, and a trench formed at the first surface. A conductive layer is formed on the first surface and in the trench. A planarizable layer comprised of a dielectric layer is then formed on the conductive layer. A handle wafer is bonded to the planarizable layer. The active wafer and the handle wafer are heated so that the doped region diffuses along the conductive layer to form an equalized concentration of dopant along the conductive layer which diffuses into the active wafer to form the doped region adjacent all of the conductive layer. A portion of the second surface of the active wafer is then removed so that at least a portion of the dielectric layer of the planarizable layer is exposed.

Method of making dielectric and conductive isolated island

An improved semiconductor die for plastic encapsulated semiconductor device packages which impedes the inherent delamination caused by the differing expansion coefficients of the semiconductor die and plastic encapsulation. Rounded or tapered die corners and die edges decrease the stress from the plastic encapsulation that acts upon the semiconductor die. This reduced stress slows the delamination progression and leaves the operational circuitry unaffected for an increased period of time thereby increasing device lifetime.

Semiconductor die having rounded or tapered edges and corners

An improved semiconductor die for plastic encapsulated semiconductor devices which impedes the inherent delamination caused by the differing expansion coefficients of the semiconductor die and plastic encapsulation. Topological configurations are processed in the die corners of the semiconductor die which are void of circuitry. The topological configurations act as barriers and slow the delamination progression. This leaves the operational circuitry unaffected for an increased time thereby increasing device lifetime.

Die corner design having topological configurations

A molded semiconductor package having a flagless leadframe wherein a semiconductor die is disposed in or above a die opening of a leadframe. This allows for thin, symmetrical packages and packages having a minimum number of material interfaces to be manufactured because no leadframe flags and minimal die bond material are employed. The present invention further includes guard rings to protect high stress areas of the semiconductor die from damage and heat spreaders to more effectively spread heat dissipated by the semiconductor die.

Flagless semiconductor package

Growing community of inventors

Phoenix, AZ, United States of America

Israel A Lesk