Intel Corporation

University of Central Florida Research Foundation Inc

Other

Islam A Salama

Yonggang Li

Robert L Sankman

Robert Alan May

Charan K Gurumurthy

Kristof Darmawikarta

Sri Ranga Sai Boyapati

Mihir K Roy

Amruthavalli Pallavi Alur

Nathaniel R Quick

Aravinda Kar

Houssam Jomaa

Yongki Min

Tao Wu

Wei-Lun Kane Jen

Huankiat Seh

Johanna M Swan

Kyu Oh Lee

Omar James Bchir

Sheng C Li

Chong Zhang

Hamid Azimi

Feras Eid

Sasha N Oster

Ravi Kiran Nalla

Mark S Hlad

Kyu-Oh Lee

Yueli Liu

Jonathan Rosch

Uygar E Avci

Kemal Aygun

Omkar G Karhade

Nitin A Deshpande

John Stephen Guzek

William J Lambert

Ram S Viswanath

Sri Chaitra Jyotsna Chavali

Stefanie M Lotz

Charles A Gealer

Christopher J Nelson

Charavana K Gurumurthy

Tyler N Osborn

Amruthavalli Palla Alur

Babak Sabi

Ravi Tanikella

Grant A Crawford

Ravi Pillarisetty

Srinivas V Pietambaram

Rahul N Manepalli

Rahul Jain

Dilan Seneviratne

Yikang Deng

Javier Soto Gonzalez

Amanda E Schuckman

Siddharth K Alur

Qinglei Zhang

Haifa Hariri

Sri Chaitra Chavali

Zheng Zhou

Lay Wai Kong

Ravi Pallarisetty

Sri Ranga Boyapati

Nikhil Sharma

A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

Microelectronic device with embedded die substrate on interposer

A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

Device and method of very high density routing used with embedded multi-die interconnect bridge

An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.

Embedded multi-die interconnect bridge packages with lithographically formed bumps and methods of assembling same

Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes.

Methods to pattern TFC and incorporation in the ODI architecture and in any build up layer of organic substrate

Embodiments include semiconductor packages. A semiconductor package includes a first patch and a second patch on an interposer. The semiconductor package also includes a first substrate in the first patch, and a second substrate in the second patch. The semiconductor package further includes an encapsulation layer over and around the first and second patches, a plurality of build-up layers on the first patch, the second patch, and the encapsulation layer, and a plurality of dies and a bridge on the build-up layers. The bridge may be communicatively coupled with the first substrate of the first patch and the second substrate of the second patch. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first and second substrates may be EMIBs and/or high-density packaging (HDP) substrates. The bridge may be positioned between two dies, and over an edge of the first patch and an edge of the second patch.

Substrate patch reconstitution options

Microelectronic devices with an embedded die substrate on an interposer are described. For example, a microelectronic device includes a substrate housing an embedded die. At least one surface die is retained above a first outermost surface of the substrate. An interposer is retained proximate a second outermost surface of the substrate.

Embedded multi-die interconnect bridge packages with lithotgraphically formed bumps and methods of assembling same

Various embodiments of the disclosure are directed to a semiconductor package and a method for fabrication of the semiconductor package. Further, disclosed herein are systems and methods that are directed to using a photoimagable dielectric (PID) layer with substantially similar mechanical properties as that of a mold material. The disclosure can be used, for example, in the context of bumpless laserless embedded substrate structures (BLESS) technology for wafer/panel level redistribution layer (RDL) and/or fan-out packaging applications. The disclosed embodiments may reduce the need for multiple dry resist film (DFR) lamination steps during various processing steps for semiconductor packaging and can also facilitate multiple layer counts due to the availability of thin PID materials.

Systems and methods for semiconductor packages using photoimageable layers

An integrated circuit (IC) structure includes a first IC package (ICP), including a first resist surface provided with a first plurality of conductive contacts (CCs), a first recess including a second resist surface disposed at a bottom of the recess and having a second plurality of CCs, and a second recess, including a third resist surface disposed at a bottom of the recess and provided with a fourth plurality of CCs. The IC structure further includes an IC component with a first surface and a second surface, the second surface having a third plurality of CCs coupled to the second plurality of CCs of the first ICP. The IC structure further includes a second ICP having a first surface and a second surface, with one or more CCs located at the second surface and coupled to at least one of the first plurality of CCs of the first ICP.

Integrated circuit structures with recessed conductive contacts for package on package

A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof, and the second supplemental patterned conductive layer at another side thereof.

Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method

Embodiments of the present disclosure are directed towards an acousto-optics deflector and mirror for laser beam steering and associated techniques and configurations. In one embodiment, a laser system may include an acousto-optics module to deflect a laser beam in a first scanning direction of the laser beam on an integrated circuit (IC) substrate when the IC substrate is in a path of the laser beam and a mirror having at least one surface to receive the laser beam from the acousto-optics module, the mirror to move to control position of the laser beam in a second scanning direction, wherein the second scanning direction is substantially perpendicular to the first scanning direction. Other embodiments may be described and/or claimed.

Acousto-optics deflector and mirror for laser beam steering

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Chandler, AZ, United States of America

Islam A Salama