Agere Systems Inc.

Lucent Technologies Inc.

Agere Systems Guardian Corp.

Other

Isik C Kizilyalli

Pradip Kumar Roy

Sailesh Mansinh Merchant

Joseph Rudolph Radosevich

Yi Ma

Ranbir Singh

Nace Layadi

Reginald Conway Farrow

David Charles Brady

Richard William Gregor

Peter Ledel Gammel

Marco Mastrapasqua

Masis Mkrtchyan

David M Boulin

Lori Stirling

Muhammed Ayman Shibib

Shuming Xu

William Thomas Cochran

Hem M Vaidya

Morgan J Thoma

Zhijian Xie

Simon John Molloy

Erik Cho Houge

Clifford Alan King

Ross Alan Kohler

Ronald Lamar Freyman

John Martin McIntosh

Hugo Fernando Safar

Omkaram Nalamasu

Catherine B Vartuli

Bailey R Jones

George Patrick Watson

Stephen Carl Kuehne

Fred Anthony Stevie

Mark Richard Pinto

Jeff Devin Bude

Thomas Edward Ham

Xiaojun Deng

Robert M Vella

Jaseph R Radosevich

Kent Smith

In a metal-oxide semiconductor device including first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, a drift region formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions, an insulating layer formed on at least a portion of the upper surface of the semiconductor layer, and a gate formed on the insulating layer and at least partially between the first and second source/drain regions, a method for controlling an amount of hot carrier injection degradation in the device includes the steps of: forming a shielding structure on the insulating layer above at least a portion of the drift region and substantially between the gate and the second source/drain region; and adjusting an amount of coverage of the shielding structure over an upper surface of the drift region so as to minimize the amount of hot-carrier injection degradation while maintaining a breakdown voltage in the device which is greater than or equal to a prescribed value.

Control of hot carrier injection in a metal-oxide semiconductor device

A method of manufacture for semiconductor electronic products and a circuit structure. A semiconductor material has a surface region and dopant is provided to a portion of the surface region. The portion of the surface region provided with the dopant is irradiated with sufficient energy to induce diffusion of the dopant from the portion of the surface region to another region of the semiconductor material. A method for manufacturing an electronic product with a semiconductor material having a surface and two spaced-apart regions along the surface for receiving dopant includes forming a field effect transistor gate structure is along the surface and over a third region of the surface between the two spaced-apart regions. Dopant is provided to the spaced-apart regions which are heated to a temperature at least 50 degrees C. higher than the peak temperature which results in the third region when the spaced-apart regions are heated. A circuit comprises a semiconductor material having a surface region for formation of devices, a field effect transistor gate structure formed on the surface region, the gate structure including a conductive layer and an amorphous insulative layer having a dielectric constant greater than five relative to free space. The insulative layer is formed between the conductive layer and the surface region. A source region is formed along the surface region and a drain region is also formed along the surface region. The gate structure, source region and drain region are configured to form an operable field effect transistor.

Selective laser annealing of semiconductor material

The present invention provides a process for manufacturing a semiconductor device that can be incorporated into an integrated circuit. The method includes, forming a first doped layer of isotopically enriched silicon over a foundational substrate, forming a second layer of an isotopically enriched semiconductor material silicon over the first doped layer, and constructing active devices on the second layer. The device includes a first doped layer of an isotopically enriched semiconductor material and a second layer of an isotopically enriched semiconductor material located over the first doped layer, and active devices located on the second layer.

Device and method using isotopically enriched silicon

An MOS device is formed including a semiconductor layer of a first conductivity type, and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A drift region is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on at least a portion of the upper surface of the semiconductor layer and above at least a portion of the drift region. A gate is formed on the insulating layer and at least partially between the first and second source/drain regions. The MOS device further includes a shielding structure formed on the insulating layer above at least a portion of the drift region. The shielding structure is configured such that an amount of hot carrier injection degradation in the MOS device is controlled as a function of an amount of coverage of the shielding structure over an upper surface of the drift region.

An MOS device is formed including a semiconductor layer of a first conductivity type, and source and drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The source and drain regions are spaced apart relative to one another. A drift region of the second conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the source and drain regions, the drift region having an impurity doping concentration greater than about 2.012 atoms/cm. An insulating layer is formed on at least a portion of the upper surface of the semiconductor layer. The device further includes a gate formed on the insulating layer at least partially between the source and drain regions, and a buried layer of the first conductivity type formed in the semiconductor layer in close relative proximity to and beneath at least a portion of the drift region. A substantially vertical distance between the buried layer and the drift region, and/or one or more physical dimensions of the buried layer are configured so as to optimize a power density of the device relative to at least one of an on-resistance and a maximum drain current of the device.

Semiconductor device having improved power density

A multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.

Multi-layered semiconductor structure

A method for dry etching a material deposited on semiconductor device is performed by chemically reacting the material with an etchant gas. The etching process is conducted in a reaction chamber at a predetermined temperature and predetermined pressure within the reaction chamber and without the need of generating a plasma within the chamber or applying an electrical bias to the semiconductor device. A sufficient amount of gas is introduced into the reaction chamber to selectively remove the material from the semiconductor device.

Method of dry etching a semiconductor device in the absence of a plasma

A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.

Method of forming an alignment feature in or on a multi-layered semiconductor structure

The present invention provides a process for fabricating merged integrated circuits on a semiconductor wafer substrate. The process comprises forming a gate oxide on the semiconductor wafer substrate, forming a first transistor having a first gate on the gate oxide, and forming a second transistor having a second gate on the same gate oxide. The first transistor is optimized to a first operating voltage by varying a physical property of the first gate, varying a first tub doping profile, or varying a first source/drain doping profile. The second transistor is optimized to a second operating voltage by varying a physical property of the second gate, varying a second tub doping profile, or varying a second source/drain doping profile of the second transistor. These physical characteristics may be changed in any combination or singly to achieve the determined optimization of the operating voltage of any given transistor.

Method for fabricating a merged integrated circuit device

A method for forming single crystalline silicon-on-insulator (SOI) structures over a silicon substrate includes forming an amorphous silicon layer over an insulating layer and contacting the substrate through the insulating layer. An excimer laser having operating conditions and a wavelength chosen to selectively melt amorphous silicon irradiates the entire substrate surface and is largely non-absorbed by materials other than silicon when incident upon them. Heating of the substrate and other materials is therefore minimal. After a blanket radiation process selectively melts the amorphous silicon layer, cooling conditions are chosen such that a single crystal silicon film is formed during the solidification process due to contact to the single crystal silicon substrate which acts as a seed layer. Various devices may be formed on the SOI islands as well as on exposed portions of the substrate not covered by the SOI islands.

Formation of silicon on insulator (SOI) devices as add-on modules for system on a chip processing

The memory element of the present invention utilizes a substrate, a first conductive connection, a second conductive connection, and an ionic layer. The substrate includes a source region, a drain region, and a channel region, which is disposed between the source region and the drain region. The ionic layer includes ions and is coupled to the substrate. The first connection is coupled to the source region, and the second connection is coupled to the drain region. An electrical field is applied through said ionic layer such that the ions in the ionic layer move. When the memory element is to exhibit a logical high state, the polarity of the electrical field causes the ions to move toward the channel region. This pulls the electrons in the source and drain regions into the channel region making the channel region conductive. When the memory element is to exhibit a logical low state, the polarity of the electrical field causes the ions to move away from the channel region. As a result, the channel region becomes non-conductive, and the first conductive connection is, therefore, insulated from the second conductive connection.

Stable memory device that utilizes ion positioning to control state of the memory device

The present invention provides a semiconductor device located on a semiconductor substrate having opposite types of first and second transistors formed thereon. The device preferably includes a first gate electrode that includes a first metal gate electrode material having a work function compatible with the first transistor, and a second gate electrode that includes a second metal gate electrode material having a work function compatible with the second transistor and the first metal gate electrode material is also located over the second metal gate electrode material, which forms a gate stack.

Semiconductor device having a metal gate with a work function compatible with a semiconductor device

Method of forming an alignment feature in or on a multilayered semiconductor structure

Method for fabricating a structure. According to an exemplary embodiment, a structure is made by forming a layer of removable material with a first surface spaced a part from a second surface. The first surface is formed along a first region from which the material is removable. The first surface is altered by removal of material from the layer. Removed material from the first surface is monitored to detect fluctuations in a variable of composition in the layer, and removal of material from the first surface is terminated when the composition of monitored material meets a predetermined criterion. In an alternate embodiment a variable characteristic is imparted to a layer of material as a function of layer thickness and an operation is performed on the layer resulting in removal of material. Samples of removed material are monitored for variation in the characteristic and the operation is modified when a variation conforms with a criterion.

Monitoring system for determining progress in a fabrication activity

Growing community of inventors

Millburn, NJ, United States of America

Isik C Kizilyalli