Arm Limited

Isidoros Sideris

Daren Croxford

Andrew Burdass

Stephane Forey

Andreas Due Engh-Halstvedt

William Robert Stoye

Reimar Gisbert Döffinger

Roko Grubisic

Nebojsa Makljenovic

John David Robson

Amir Kleen

Michel Patrick Gabriel Emil Iwaniec

Eugenia Cordero-Crespo

Péter Sonkoly

Adrian Pereiro Castro

A data processor is disclosed in which groups of execution threads comprising a thread group can execute a set of instructions in lockstep, and in which a plurality of execution lanes can perform processing operations for the execution threads. In response to an execution thread issuing circuit determining whether a portion of active threads of a first thread group and a portion of active threads of a second thread group use different execution lanes of the plurality of execution lanes, the execution thread issuing circuit issuing both the portion of active threads of a first thread group and a portion of active threads of a second thread group for execution. This can have the effect of increasing data processor efficiency, thereby increasing throughput and reducing latency.

Apparatus and method of optimizing divergent processing in thread groups preliminary class

Disclosed is a method of handling thread termination events within a graphics processor when a group of plural execution lanes are executing in a co-operative state. When a group of lanes is in the co-operative state, in response to the graphics processor encountering an event that means that a subset of one or more execution threads associated with the group of execution lanes in the co-operative state should be terminated: it is determined whether a condition to immediately terminate the subset of one or more execution threads is met. When the condition is not met, the group of execution lanes continue their execution in the co-operative state, but a record is stored to track that the threads in the subset of one or more execution threads should subsequently be terminated.

Graphics processing

There is provided a graphics processor comprising a programmable execution unit operable to execute programs for respective execution thread groups. An eviction checking circuit is provided that is configured to check instructions as they are being fetched for execution from an instruction cache to determine whether the instruction includes any conditional eviction conditions that if not met indicate that the program to which the instruction relates should not continue to be executed for the group of execution threads. The eviction checking circuit is then configured to check whether any conditional eviction conditions are satisfied at this point and either allow the execution unit to continue program execution or cause the thread group to be evicted.

Graphics processing systems with conditional evictions

An apparatus and method are provided for executing thread groups. The apparatus comprises scheduling circuitry for selecting for execution a first thread group from a plurality of thread groups, and thread processing circuitry that is responsive to the scheduling circuitry to execute active threads of the first thread group in dependence on a common program counter shared between the active threads. In response to an exit event occurring for the first thread group, the thread processing circuitry determines whether a program counter check condition is present, and this can be used to trigger program counter checking circuitry to perform a program counter check operation to update the common program counter and an active thread indication for the first thread group. The thread processing circuitry is provided with register storage in which program counter information for each thread of the first thread group can be stored, and the program counter checking circuitry is arranged to have access to that register storage when performing the program counter check operation. Further, the scheduling circuitry is arranged to select, for execution by the thread processing circuitry, a different thread group whilst awaiting performance of the program counter check operation by the program counter checking circuitry for the first thread group. This provides an area efficient mechanism for handling divergence and re-convergence of threads within thread groups, in a manner that avoids impacting performance.

Apparatus and method of executing thread groups

A warp processing unit controls, in dependence on a warp program counter shared between a plurality of threads processing respective graphics fragments, fetching of a next instruction to be executed for at least some of the plurality of threads. In response to a determination that a given subset of threads is to be discarded when at least one other subset of threads is to continue, the warp processing unit processes the given subset of threads in a discarded state. For a thread processed in the discarded state, execution of instructions continues for the discarded thread, and at least one of: generation of data access messages triggered by the discarded thread is suppressed; and at least one processing operation, which would be deferred until completion of the discarded thread had the thread not been discarded, is enabled to be commenced independently of an outcome of the discarded thread.

Discarding of threads processed by a warp processing unit

A data processing apparatus has control circuitry for detecting whether a first micro-operation to be processed by a first processing lane would give the same result as a second micro-operation processed by a second processing lane. If they would give the same result, then the first micro-operation is prevented from being processed by the first processing lane and the result of the second micro-operation is output as the result of the first micro-operation. This avoids duplication of processing, to save energy for example.

Preventing duplicate execution by sharing a result between different processing lanes assigned micro-operations that generate the same result

A graphics processing apparatus and method of performing graphics processing are provided. The graphics processing apparatus comprises a sequence of processing stages capable of performing graphics processing to generate a frame of display data. The graphics processing is performed on a tile-by-tile basis. The graphics processing apparatus is capable of determining if a current tile subject to the graphics processing is empty. At least one processing stage of the sequence of processing stages is omitted for graphics processing of the current tile in dependence on whether the current tile is empty.

Tile based graphics processor and a method of performing graphics processing in a tile based graphics processor

A data processing apparatus has control circuitry for detecting whether a current micro-operation to be processed by processing circuitry is for the same data processing operation and specifies the same at least one operand as the last valid micro-operation processed by the processing circuitry. If so, then the control circuitry prevents the processing circuitry processing the current micro-operation so that an output register is not updated in response to the current micro-operation, and outputs the current value stored in the output register as the result of the current micro-operation. This allows power consumption to be reduced or performance to be improved by not repeating the same computation.

Reuse of results of back-to-back micro-operations

A data processing apparatus has control circuitry for detecting whether a current micro-operation to be processed by a processing pipeline would give the same result as an earlier micro-operation. If so, then the current micro-operation is passed through the processing pipeline, with at least one pipeline stage passed by the current micro-operation being placed in a power saving state during a processing cycle in which the current micro-operation is at that pipeline stage. The result of the earlier micro-operation is then output as a result of said current micro-operation. This allows power consumption to be reduced by not repeating the same computation.

Power saving by reusing results of identical micro-operations

Address translation circuitry and a method of operating such a translation circuitry are provided. The address translation circuitry is configured to receive a first address used in a first addressing system and to translate it into a second address used in a second addressing system. Translation pipeline circuitry has plural pipeline stages configured to translate the first address into the second address over the course of the plural pipeline stages. Address comparison circuitry is configured to identify an address match condition when a received first address at least partially matches a previously received first address. Insertion circuitry is configured to determine a stage of progress of the previously received first address in the plural pipeline stages and to cause content of the stage of progress of the previously received first address to be unchanged at a next pipeline cycle when the address comparison circuitry identifies the address match condition.

Growing community of inventors

Cambridge, United Kingdom

Isidoros Sideris