Intel Corporation

Ishwar Bhati

Subramaniam M Maiyuran

Varghese George

Guei-Yuan Lueh

Sreenivas Subramoney

Dipankar Das

Jorge E Parra

Wei-Yu Chen

Supratim Pal

Chandra S Gurram

Ashutosh Garg

Jayesh Gaur

Sasikanth Avancha

Junjie Gu

Sudarshan Srinivasan

Sasikanth Manipatruni

Ian A Young

Hong Wang

Tanay Karnik

Zeshan A Chishti

Huichu Liu

Kunal Korgaonkar

Udit Dhawan

Embodiments described herein provide for an instruction and associated logic to enable a vector multiply add instructions with automatic zero skipping for sparse input. One embodiment provides for a general-purpose graphics processor comprising logic to perform operations comprising fetching a hardware macro instruction having a predicate mask, a repeat count, and a set of initial operands, where the initial operands include a destination operand and multiple source operands. The hardware macro instruction is configured to perform one or more multiply/add operations on input data associated with a set of matrices.

Instructions and logic for vector multiply add with zero skipping

Processor, apparatus, and method for reordering a stream of memory access requests to establish locality are described herein. One embodiment of a method includes: storing in a request queue memory access requests generated by a plurality of execution units, the memory access requests comprising a first request to access a first memory page in a memory and a second request to access a second memory page in the memory; maintaining a list of unique memory pages, each unique memory page associated with one or more memory access requests stored the request queue and is to be accessed by the one or more memory access requests; selecting a current memory page from the list of unique memory pages; and dispatching from the request queue to the memory, all memory access requests associated with the current memory page before any other memory access request in the request queue is dispatched.

Memory aware reordered source

A processor includes a processing core and a cache controller including a read queue and a separate write queue. The read queue is to buffer read requests of the processing core to a non-volatile memory, last level cache (NVM-LLC), and the write queue is to buffer write requests to the NVM-LLC. The cache controller is to detect whether the write queue is full. The cache controller further prioritizes a first order of sending requests to the NVM-LLC when the write queue contains an empty slot, the first order specifying a first pattern of sending the read requests before the write requests, and prioritizes a second order of sending requests to the NVM-LLC in response to a determination that the write queue is full, the second order specifying a second pattern of alternating between sending a write request from the write queue and a read request from the read queue.

Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein the threshold is derived from latency of write to LLC and main memory retrieval time

Provided are a memory system, device, and method for determining to send a refresh command to a memory module according to a refresh rate and incrementing a postponed refresh count while the memory module is in an active mode in response to the determining to send the refresh command. The refresh command is not sent to the memory module when the postponed refresh count is incremented. A determination is made as to whether the postponed refresh count exceeds a count threshold. A refresh command is issued to the memory module to perform refresh in an active mode in response to determining that the postponed refresh count exceeds the count threshold.

Coordinating power mode switching and refresh operations in a memory device

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Bengaluru, India

Ishwar Bhati