Intel Corporation

Microsoft Technology Licensing, LLC

Ishwar Agarwal

Stephen R Van Doren

Rajesh M Sankaran

George Zacharias Chrysos

David J Harriman

Kirk S Yap

Siamak Tavallaei

Yevgeniy Bak

Alastair Wolman

Stefan Saroiu

Mahesh U Wagh

Mark A Schmisseur

Venkatraman Iyer

Raj K Ramanujan

Yen-Cheng Liu

Ioannis T Schoinas

Raghunandan Makaram

Rupin H Vakharwala

Pratik M Marolia

Zuoguo Wu

Joseph Nuzman

Ashok Raj

Gerald S Pasdast

David A Koufaty

Bryan David Kelly

Su Wei Lim

Gideon Gerzon

Vishal Soni

Nitish Paliwal

Oscar Rosell Martinez

Rahul Pal

Daniel Sebastian Berger

Lisa Ru-feng Hsu

Sean O Stalley

Peeyush Purohit

Ramacharan Sundararaman

Manoj K Arora

Janaina Barreiro Gambaro Bueno

Archana Srinivasan

Aninda Manocha

Ashish Gupta

Bahaa Fahim

Chandan Egbert

David M Lee

Theodros Yigzaw

Bharat S Pillilli

Andreas Kleen

Mark S Birrittella

Mohan Nair

Amin Firoozshahian

Mahesh Srinivasa Maddury

Omid Azizi

Vivekananthan Sanjeepan

Ashok Jagannathan

Alexandre Y Solomatnikov

Andy M Rudoff

Mahesh Madhav

Stanko Novakovic

David Hansen

Lisa Ru-Feng Hsu

Lip Khoon Teh

Nithiyanandan Bashyam

Filip Schmole

Anoop Kumar Upadhyay

Vijay Pothi Raj Govindaraj

Rahul Boyapati

Minjer Juan

A circuit system includes slow running logic circuitry that generates write data and a write command for a write request. The circuit system also includes fast running logic circuitry that receives the write data and the write command from the slow running logic circuitry. The fast running logic circuitry stores the write data and the write command. A host system generates a write response in response to receiving the write command from the fast running logic circuitry. The host system sends the write response to the fast running logic circuitry. The fast running logic circuitry sends the write data to the host system in response to receiving the write response from the host system before providing the write response to the slow running logic circuitry.

Circuits and methods for coherent writing to host systems

A computing device includes a system-on-a-chip. The computing device comprises a network interface controller (NIC) that hosts a plurality of virtual functions and physical functions. Two or more compute nodes are coupled to the NIC. Each compute node is configured to operate a plurality of Virtual Machines (VMs). Each VM is configured to operate in conjunction with a virtual function via a virtual function driver. A dedicated VM operates in conjunction with a virtual NIC using a physical function hosted by the NIC via a physical function driver hosted by the compute node. The computing device further comprises a fabric manager configured to own a physical function of the NIC, to bind virtual functions hosted by the NIC to individual compute nodes, and to pool I/O devices across the two or more compute nodes.

Computing device with independently coherent nodes

Systems and methods for a confidential compute architecture integrated with direct swap caching are described. An example method for managing a near memory and a far memory includes, in response to determining that the far memory contains an encrypted version of a first block of data, retrieving from the far memory the encrypted version of the first block of data, decrypting the first block of data using a first key for exclusive use by a first virtual machine associated with the system, and providing a decrypted version of the first block of data to the requestor. The method further includes swapping out a second block of data having an address conflict with the first block of data from the near memory to the far memory, where the second block of data is encrypted using a second key for exclusive use by a second virtual machine associated with the system.

Confidential compute architecture integrated with direct swap caching

Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

Non-posted write transactions for a computer bus

A method for memory address mapping in a disaggregated memory system includes receiving an indication of one or more ranges of host physical addresses (HPAs) from a compute node of a plurality of compute nodes, the one or more ranges of HPAs including a plurality of memory addresses corresponding to different allocation slices of the disaggregated memory pool that are allocated to the compute node. The one or more ranges of HPAs are converted into a contiguous range of device physical addresses (DPAs). For each DPA, a target address decoder (TAD) is identified based on a slice identifier and a slice-to-TAD index. Each DPA is mapped to a media-specific physical element of a physical memory unit of the disaggregated memory pool based on the TAD.

Addressing for disaggregated memory pool

The present disclosure relates to systems and methods implemented on a memory controller for detecting and mitigating memory attacks (e.g., row hammer attacks). For example, a memory controller may engage a counting mode in which activation counts for memory sub-banks are tracked. For example, a memory controller may engage a counting mode in which activation counts for memory rows of memory sub-banks are maintained. Under certain conditions, the memory controller may transition from the counting mode to a sampling mode to mitigate potential row hammer attacks. The memory controller may consider various conditions in determining whether to continue detecting and mitigating potential row hammer attacks in the sampling mode and/or transitioning back to the counting mode. By selectively transitioning between the different operating modes, the memory controller may reduce periods of time when the memory hardware is vulnerable to attacks.

Detecting and mitigating memory attacks

Systems and methods related to flush plus reload cache side-channel attack mitigation are described. An example method for mitigating a side-channel timing attack in a system including a processor having at least one cache is described. The method includes receiving a first instruction, where the first instruction, when executed by the processor, is configured to flush at least one cache line from the at least one cache associated with the processor. The method further includes, prior to execution of the first instruction by the processor, automatically mapping the first instruction to a second instruction such that the at least one cache line is not flushed from the at least one cache even in response to receiving the first instruction.

Systems and methods for flush plus reload cache side-channel attack mitigation

Disclosed herein is a thin-provisioned multi-node computer system with a disaggregated memory pool and a pooled memory controller. The disaggregated memory pool is configured to make a shared memory capacity available to each of a plurality of compute nodes, such memory capacity being thinly provisioned relative to the plurality of compute nodes. The pooled memory controller is configured to assign a plurality of memory segments of the disaggregated memory pool to the plurality of compute nodes; identify a subset of the plurality of segments as cold segments, such identification being based on determining that a usage characteristic for each such cold segment is below a threshold; and page one or more of the cold segments out to an expanded bulk memory device, thereby freeing one or more assigned memory segments of the disaggregated memory pool.

Paging in thin-provisioned disaggregated memory

Systems and methods related to direct swap caching with zero line optimizations are described. A method for managing a system having a near memory and a far memory comprises receiving a request from a requestor to read a block of data that is either stored in the near memory or the far memory. The method includes analyzing a metadata portion associated with the block of data, the metadata portion comprising: both (1) information concerning whether the near memory contains the block of data or whether the far memory contains the block of data and (2) information concerning whether a data portion associated with the block of data is all zeros. The method further includes instead of retrieving the data portion from the far memory, synthesizing the data portion corresponding to the block of data to generate a synthesized data portion and transmitting the synthesized data portion to the requestor.

Direct swap caching with zero line optimizations

Techniques of memory tiering include retrieving, from a first tier in a first memory, data from a data portion and metadata from a metadata portion of the first tier upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first tier currently contains data corresponding to the system memory section in the received request. In response to determining that the first tier currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the first or second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.

Memory tiering techniques in computing systems

The present disclosure relates to systems and methods implemented on a memory controller for detecting and mitigating memory attacks (e.g., row hammer attacks). For example, a memory controller may track activations of row addresses within a memory hardware (e.g., a DRAM device) and determine whether a pattern of activations is indicative of a row hammer attack. This is determined using a counting mode for corresponding memory sub-banks. Where a likely row hammer attack is detected, the memory controller may activate a sampling mode (rather than the counting mode) for a particular sub-bank to identify which of the row addresses should be refreshed on the memory hardware. The implementations described herein provide a low computational cost alternative to heavy-handed detection mechanisms that require access to significant computing resources to accurately detect and mitigate row hammer attacks.

Systems and methods related to integrated memory pooling and direct swap caching are described. A system includes a compute node comprising a local memory and a pooled memory. The system further includes a host operating system (OS) having initial access to: (1) a first swappable range of memory addresses associated with the local memory and a non-swappable range of memory addresses associated with the local memory, and (2) a second swappable range of memory addresses associated with the pooled memory. The system further includes a data-mover offload engine configured to perform a cleanup operation, including: (1) restore a state of any memory content swapped-out from a memory location within the first swappable range of memory addresses to the pooled memory, and (2) move from the local memory any memory content swapped-in from a memory location within the second swappable range of memory addresses back out to the pooled memory.

Systems and methods with integrated memory pooling and direct swap caching

The present disclosure relates to systems, methods, and computer-readable media for tracking memory usage data on a memory controller system and providing a mechanism whereby one or multiple accessing agents (e.g., computing nodes, applications, virtual machines) can access memory usage data for a memory resource managed by a memory controller. Indeed, the systems described herein facilitate generation of and access to heatmaps having memory usage data thereon. The systems described herein describe features and functionality related to generating and maintaining the heatmaps as well as providing access to the heatmaps to a variety of accessing agents. This memory tracking and accessing is performed using low processing overhead while providing useful information to accessing agents in connection with memory resources managed by a memory controller.

Managing and ranking memory resources

Systems and methods related to direct swap caching with noisy neighbor mitigation and dynamic address range assignment are described. A system includes a host operating system (OS), configured to support a first set of tenants associated with a compute node, where the host OS has access to: (1) a first swappable range of memory addresses associated with a near memory and (2) a second swappable range of memory addresses associated with a far memory. The host OS is configured to allocate memory in a granular fashion such that each allocation of memory to a tenant includes memory addresses corresponding to a conflict set having a conflict set size. The conflict set includes a first conflicting region associated with the first swappable range of memory addresses with the near memory and a second conflicting region associated with the second swappable range of memory addresses with the far memory.

Direct swap caching with noisy neighbor mitigation and dynamic address range assignment

Growing community of inventors

Redmond, WA, United States of America

Ishwar Agarwal