Tower Semiconductor Ltd.

Ishai Nachumovsky

Robert J Strain

Yaov Nissan-Cohen

Yoav Lavi

A test system includes a test wafer having non-volatile memory dies and an exposed set of pads. A probe wafer includes test circuitry, a first set of pads exposed at a first surface, a second set of pads exposed at a second surface (opposite the first surface), and an interconnect structure. The interconnect structure includes traces that extend through the probe card or around the edges of the probe card, between the first and second surfaces. A prober aligns the test wafer with the probe wafer, such that the pads of the test wafer contact the first set of pads of the probe wafer. The prober further contacts the second set of pads of the probe wafer, and provides connections between these pads and a tester. The probe wafer is fabricated using semiconductor processing techniques, so that precise alignment exists between the test wafer and the probe wafer.

Efficient test structure for non-volatile memory and other semiconductor integrated circuits

A multi-bit programmable memory cell is provided that includes an access transistor and a plurality of N anti-fuse elements. The access transistor has a source coupled to a source line and a gate coupled to a word line. Each of the anti-fuse elements has a first terminal coupled to a drain of the access transistor, and a second terminal coupled to a corresponding bit line. At most, only one of the anti-fuse elements is programmed. The memory cell is capable of storing M bits, wherein N&equals;2 &minus;1. A method is provided for both programming and reading the memory cell. In another embodiment, the anti-fuse elements can be replaced with mask-programmable elements.

Mask programmable read-only memory (ROM) cell

Multi-bit programmable memory cell having multiple anti-fuse elements

A structure and method for implementing an EEPROM using 2-bit non-volatile memory cells. Each memory cell has a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit. The memory cells are arranged in one or more rows, with a word line coupling the gates of all of the memory cells in each row. Diffusion bit lines couple the first charge trapping region of each memory cell with the second charge trapping region of an adjacent memory cell. When the first charge trapping region of a memory cell is erased, the second charge trapping region of the adjacent memory cell is incidentally erased. This incidental erasure is effectively avoided by: (1) reading the bit stored in the second charge trapping region, (2) writing this bit to a storage device, (3) performing the erase operation, and then (4) restoring the bit from the storage device to the second charge trapping region of the adjacent memory cell. If an erase operation results in the incidental erasure of additional bits (as will occur when more than one row of memory cells is coupled to a single diffusion bit line), then all of the bits that would be incidentally erased are written to the storage device before the erase operation, and are restored to the array after the erase operation. The incidental erasure can also be rendered moot by using only one charge trapping region of each memory cell.

EEPROM array using 2-bit non-volatile memory cells and method of implementing same

A memory circuit that includes a series of parallel elongated diffusion bit lines and an array of 2-bit non-volatile memory cells connected between the diffusion bit lines. Column select circuits are located at the ends of the diffusion bits lines that selectively connect the diffusion bit lines to a bit line decoder circuit to read appropriate signals from selected memory cells. A series of metal jumpers extend over and connect the ends of the diffusion bit lines. By connecting both ends of the diffusion bit lines together, the metal jumpers allow the diffusion bit lines to be longer without increasing resistance, so that a single pair of column select circuit control a large number of memory cells to increase the area efficiency of the memory array. Conversely, the metal jumpers reduce the resistance in shorter diffusion bit lines, thereby increasing memory array endurance.

Area efficient column select circuitry for 2-bit non-volatile memory cells

A structure and method for implementing an EEPROM array using 2-bit non-volatile memory cells arranged in a plurality of rows and columns. Each memory cell has a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit. A plurality of bit lines are provided, wherein each bit line is coupled to the first charge trapping region of each memory cell in one column and to the second charge trapping region of each memory cell in an adjacent column. A memory control circuit is coupled to the bit lines, wherein the memory control circuit erases a word stored in the EEPROM array by applying an erase voltage to one or more of the bit lines. The applied erase voltage erasing all of the charge trapping regions coupled to the one or more bit lines. All of the charge trapping regions erased in response to the erase voltage represent a single word of the EEPROM array. The memory control circuit reads a word stored in the EEPROM array by sequentially accessing all of the charge trapping regions coupled to one or more of the bit lines. Similarly, the memory control circuit writes a word to the EEPROM array by sequentially programming all of the charge trapping regions coupled to one or more of the bit lines.

EEPROM array using 2-bit non-volatile memory cells with serial read operations

A semiconductor process, which creates a semiconductor devices that includes logic transistors fabricated in a first region and a fieldless array fabricated in a second region, is provided. Both the logic transistors and the fieldless array transistors have gates comprising a polysilicon layer with a silicide layer. The logic transistors have self-aligned silicide regions formed on their source and drain regions. Self-aligned silicide regions are not formed on the source and drain regions of the fieldless array transistors, thereby preventing undesirable electrical shorts which could otherwise occur within the fieldless array. The silicide structures can be fabricated by depositing polysilicon over the first and second regions, etching the polysilicon layer in the first region to define gates of the logic transistors, depositing and reacting a refractory metal, removing the non-reacted refractory metal, and then patterning the polysilicon and silicide in the second region to define gates of the fieldless array transistors.

Semiconductor chip having fieldless array with salicide gates and methods for making same

A circuit and method increases the endurance of memory cells in a memory array by decreasing the number of times a memory cell is programmed or erased. A bit-wise program/erase controller coupled to the memory array modifies the erasing and programming of multi-bit data words by erasing only those memory cells which must be erased and programming only those memory cells which must be programmed. Specifically, the bit-wise program/erase controller compares a new data word, which will be written into the memory array at a write address, with the current data word at the write address. The memory cells at the write address are categorized into a first subset and a second subset. The first subset of memory cells are currently in a programmed state but must be erased because the corresponding bit of the new data word is at an erased logic level. The second subset of memory cells are currently in an erased state but must be programmed because the corresponding bit of the new data word is at a programmed logic level. Bit-wise program/erase controller erases only the first subset of memory cells and programs only the second subset of memory cells. Thus, over multiple writes into the memory array, the number times each memory cell is erased or programmed is reduced resulting in greater endurance of the memory cells.

Program/erase endurance of EEPROM memory cells

A structure and method for configuring an EEPROM having an array of 2-bit non-volatile memory transistors to perform either in a high-speed 1-bit operation mode or a high-density 2-bit operation mode. Each memory transistor has a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit. The selected operation mode is determined by configuration data set by the EEPROM manufacturer in accordance with a customer's requirements. In one embodiment, an EEPROM includes blocks of memory cells accessed by a single word line. When the configuration data indicates the 1-bit operation mode, the memory control circuit stores data in only one of the two charge trapping regions of each memory cell. All eight bits of a word are read simultaneously by accessing eight separate charge trapping regions. Conversely, when the configuration data indicates the 2-bit operation mode, the memory control circuit stores data in both charge trapping regions of each memory cell. A read operation in the 2-bit operation mode requires reading a first group of four bits during a first stage, and then reading a second group of four bits during a second stage. These first and second groups of bits are successively stored in a shift register, and then transmitted to an I/O control circuit.

Growing community of inventors

Zichron Yaakov, Israel

Ishai Nachumovsky