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San Jose, CA, United States of America

Ish Chadha

Average Co-Inventor Count = 2.08

ph-index = 2

The patent ph-index is calculated by counting the number of publications for which an author has been cited by other authors at least that same number of times.

Forward Citations = 14

Ish ChadhaSeema Kumar (6 patents)Ish ChadhaAdithya Hrudhayan Krishnamurthy (4 patents)Ish ChadhaAbhijith Kashyap (2 patents)Ish ChadhaVirendra Kumar (2 patents)Ish ChadhaVipul Katyal (2 patents)Ish ChadhaShantanu Sarangi (1 patent)Ish ChadhaRobert Bloemer (1 patent)Ish ChadhaMahmut Yilmaz (1 patent)Ish ChadhaHao-Yi Wei (1 patent)Ish ChadhaNithin Anil Valentine (1 patent)Ish ChadhaIsh Chadha (15 patents)Seema KumarSeema Kumar (7 patents)Adithya Hrudhayan KrishnamurthyAdithya Hrudhayan Krishnamurthy (4 patents)Abhijith KashyapAbhijith Kashyap (3 patents)Virendra KumarVirendra Kumar (3 patents)Vipul KatyalVipul Katyal (3 patents)Shantanu SarangiShantanu Sarangi (24 patents)Robert BloemerRobert Bloemer (11 patents)Mahmut YilmazMahmut Yilmaz (9 patents)Hao-Yi WeiHao-Yi Wei (2 patents)Nithin Anil ValentineNithin Anil Valentine (2 patents)
..
Inventor’s number of patents
..
Strength of working relationships

Company Filing History:

1. Nvidia Corporation (15 from 5,456 patents)


15 patents:

1. 12477398 - Method and system for transmitting in-band cross-chip triggers to maintain high-speed interconnect

2. 12461880 - Test data transfer in multi-die systems

3. 12443555 - Frame alignment recovery for a high-speed signaling interconnect

4. 12405629 - High-speed signaling system with ground referenced signaling (GRS) over substrate

5. 12395311 - Reliable link management for a high-speed signaling interconnect

6. 12353271 - Error rate interrupts in hardware for high-speed signaling interconnect

7. 12027198 - Mitigating duty cycle distortion degradation due to device aging on high-bandwidth memory interface

8. 11956342 - Reliable link management for a high-speed signaling interconnect

9. 11936379 - Digital delay line calibration with duty cycle correction for high bandwidth memory interface

10. 11899609 - Frame alignment recovery for a high-speed signaling interconnect

11. 11880265 - Error rate interrupts in hardware for high-speed signaling interconnect

12. 11784890 - Link training through handshake on high-speed interconnect

13. 11575494 - Link status detection for a high-speed signaling interconnect

14. 11569939 - Synchronizing a high-speed signaling interconnect

15. 10317459 - Multi-chip package with selection logic and debug ports for testing inter-chip communications

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