Fujitsu Corporation

Fujitsu Vlsi Limited

Isaya Sobue

Hajime Sato

Hiroshi Yamamoto

Hidenori Nomura

Kenji Nagai

Akihiro Iwase

Akira Sugiura

Masami Nakashima

Tohru Yasuda

Mikio Ishikawa

Chiaki Furukawa

Seiji Yamamoto

Hirosuke Koumyoji

A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW-SWconnected between input/output pads P-Pand a testing line Lso that pads in an arbitrary combination, among the off-probe pads P-Pthat are not made in contact with the tester probe Pr, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad Pthat is made in contact with the tester probe Pr, and the leak current of the probes is measured with the tester TS.

Semiconductor device and test method for the same

A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW-SWconnected between input/output pads P-Pand a testing line Lso that pads in an arbitrary combination, among the off-probe pads P-Pthat are not made in contact with the tester probe Prare selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad Pthat is made in contact with the tester probe Prand the leak current of the probes is measured with the tester TS.

A semiconductor memory device is disclosed, which is supplied with power from a power supply and which includes memory cells and a sense amplifier connected to the cells via bit lines. The memory device further includes a circuit for enabling the sense amplifier in response to a supplied enable signal, and for allowing the sense amplifier to rewrite cell data, read on the bit lines, into the memory cell again in self-refresh mode. The enabling circuit incorporates a noise suppression circuit which suppresses rapid changes in an operation current flowing between the power supply and the sense amplifier in order to minimize power supply related noise.

Semiconductor memory device

In a semiconductor memory device with redundant configuration, a redundant address detection circuit is additionally provided between an I/O buffer and a read/write circuit coupled to a memory cell array. The detection circuit receives both a signal indicating the detection of redundancy from a redundant address setter and a signal instructing a test mode for the memory device, and selectively inverts the logic of data associated with the redundant cell. When the data is supplied to memory cells through the redundant address detection circuit under test mode conditions, only data involved in a redundant address is inverted in logic and is written into a redundant cell. Subsequently, a tester reads out the write data of all memory cells to produce a bit map indicating the address of the inverted data and allowing the tester to detect the address of redundant memory cells.

Growing community of inventors

Kasugai, Japan

Isaya Sobue