Hitachi, Ltd.

Taiyo Yuden Co., Ltd.

Other

Renesas Technology Corp.

Japan Science and Technology Agency

Nippon Zeon Company, Ltd.

Japan Synthetic Rubber Co., Ltd.

Advanced Technology Research Corporation

Isao Shimizu

Masayuki Satou

Masayuki Sato

Yasuhiro Matsuda

Takashi Yoshida

Hiroshi Fukiage

Akira Shimizu

Masashi Yoshida

Katsumi Watanabe

Kazuji Yamada

Yasuo Nagai

Hideaki Takahashi

Hideki Tanaka

Hiroshi Ikeda

Ryoichi Kobayashi

Tsuyoshi Takahashi

Kanji Kawakami

Kenji Kaneko

Yoshikazu Saitoh

Toshihiko Gotoh

Hiroshi Saito

Shinobu Yoshida

Fumio Takeda

Fujio Tajima

Atsushi Ichikawa

Takeaki Okabe

Jiro Tsuji

Takashi Kohno

Masatoshi Kimura

Seiji Aotani

Mitsunori Katsu

Kazuo Hoya

Takahiro Saito

Shozo Saekusa

Koutarou Tanno

Takashi Isago

Koushi Sato

Koozoo Sakamoto

Yoshiko Kawabe

Seiichi Katoh

Akira Ikuma

Main memory access from a CPU is reduced, and thus an increase in speed of data processing is achieved. Provided is a reconfigurable device () connected to a main memory (). The reconfigurable device () includes a plurality of logic sections connected to each other by an address line or a data line. Each of the logic sections includes a plurality of address lines, a plurality of data lines, an address decoder that decodes addresses input from part of the plurality of address lines, and a memory cell array unit that includes a plurality of memory cells specified by decode lines of the address decoder, and outputs data read from the specified memory cells to the data lines. An address line of the memory cell array unit is connected to a data output line (RD) of the main memory.

Reconfigurable device

There is provided a logic device including memory cell units. Each of the memory cell units includes a pair of bit lines arranged corresponding to a column of memory cells, a word line, and an inverter unit connected to the pair of bit lines. The inverter unit includes a first CMOS and a second CMOS. The first CMOS is configured to receive an input signal from one of the pair of bit lines. The first CMOS includes a first MOS transistor and a second MOS transistor. The second CMOS is configured to receive an input signal from the other of the pair of bit lines. The second CMOS includes a third MOS transistor and a fourth MOS transistor. The inverter unit is configured to output a first differential signal and a second differential signal as a data signal.

Reconfigurable logic device configured as a logic element or a connection element

There is provided a reconfigurable semiconductor device including a plurality of logic units connected to each other using an address line or a data line, each logic unit including a plurality of address lines, a plurality of data lines, a clock signal line configured to receive a system clock signal, a delay element configured to delay the system clock signal, a memory cell unit configured to operate in synchronization with a clock signal, and an address decoder configured to decode an address signal to output the decoded signal to the memory cell unit. The logic unit configuring a combination logic circuit operates in synchronization with a delayed clock signal outputted from the delay element.

Reconfigurable semiconductor device

There is provided a reconfigurable semiconductor device including a plurality of circuit blocks each including a reconfigurable logic unit, and an analog circuit configured to convert an analog signal from the outside into a digital signal to output the digital signal to the reconfigurable logic unit, and convert a digital signal outputted from the reconfigurable logic unit into an analog signal to output the analog signal to the outside. The circuit block has a rectangular shape, is connected to the two adjacent circuit blocks from one side with a plurality of analog lines, and is connected to the other two adjacent circuit blocks from the other side on a side opposite to the one side with a plurality of analog lines.

A reconfigurable logic device includes logic units and allows logic circuits to be formed according to configuration data. The logic units each include a configuration memory that stores first and second configuration data, a first address input line through which a clock is inputted as a first address for the configuration memory, a second address input line through which an input of a data input line is inputted as a second address for the configuration memory, a register unit that, according to the clock, reads the second configuration data specified by the first address from the configuration memory and retains the second configuration data, and outputs the first configuration data in a previous state, and a multiplexer that, according to the first or second configuration data outputted from the register unit, selectively combines a data input from the data input line and a data output to a data output line.

Reconfigurable logic device

Provided is a logic configuration method for a semiconductor device having a plurality of memory units provided with a plurality of memory cells; each memory unit is configured to store truth table data in the memory cells thereof, the truth table data being for outputting a logic value in response to an address input, and to operate as a logic circuit; the memory units have n (where n is 2 or a higher integer) times two pairs of an input line and an output line; the n times two output lines from one memory unit among the memory units are connected to the n input lines of two other memory units; and the logic configuration method generates, on the basis of the circuit description describing the circuit configuration, a netlist having circuit connection information, extracts a logic cone from the netlist, and generates truth table data for the plurality of memory units, which constitute the logic cone, in the memory unit stage number corresponding to the number obtained by dividing the number of input lines to the logic cone by n/2.

Logic configuration method for reconfigurable semiconductor device

[Problem] To be able to provide a reconfigurable logic device having a small area and enhanced reprogramming characteristics. [Solution] A reconfigurable logic device for forming a plurality of logic circuits in accordance with configuration data information. Each of the multi-lookup table units includes: a configuration memory that stores configuration data; data input lines; data output lines; and a reconfigurable logic multiplexer that, in response to the configuration data, selectively links data inputted to the data input lines to data outputted to the data output lines, and/or outputs, to the data output lines, data obtained by performing a logical operation on data pertaining to the inputted data. The multi-lookup tables that are adjacent to one another are connected through the data input lines and the data output lines of the respective multi-lookup table units.

An image checking process wherein only a defective or differential portion of a checked image is displayed together with its position and wherein no pre-processing is required for image positioning. A computer () captures a reference image or Fourier transformed image thereof from a storage part, a CCD camera () or a CCD camera () to acquire intensity information and phase information, and also captures an identified image or Fourier transformed image thereof from the storage part, CCD camera () or CCD camera () to acquire intensity information of the Fourier transformed image of the identified image. Then, the computer () determines the difference in intensity information between the reference image and the Fourier transformed image of the identified image and further determines an inverse Fourier transformed image of an expression obtained from the determined differential intensity information and the phase information of the reference image to output the inverse Fourier transformed image to an output part or display part. The inverse Fourier transformed image is used to extract, as a difference between the identified image and the reference image, an image defect of the identified image or the image difference between the identified image and the reference image.

Method and apparatus for image inspection

A database system that accommodates any type of phenomenon or thing, with a simple table structure and an extremely small-scale program. Category identification information of the content to be registered, item names that represent an attribute and/or a function included in the category, and attributes of data representing the substantial contents of these items (item data attributes) are registered in each data cell of a data property table ( ) in units of rows, and category identification information, title names, and substantial contents associated with each item are registered in data cells of a main data table ( ) in units of rows. The item names of the table ( ) and the substantial contents of the table ( ) correspond by means of cell numbers, and when a database management system ( ) performs data input, storage, searching, and output, the various methods are generated with row-direction data of the table ( ) as a message.

Database system

A test circuit is provided on a probe card or a wafer on which semiconductor chips to be tested are formed. The test circuit and each of the semiconductor chips to be tested are electrically connected to each other to perform testing, whereby the test can be carried out without using a tester. Conducting a test in such a wafer stage within an aging device allows the simplification or omission of a test subsequent to packaging.

Test system and manufacturing of semiconductor device

A semiconductor integrated circuit (FPLA) having a desired logical function achieved by arranging on a semiconductor chip variable logical circuits each having n&times;n (e.g., four) memory cells alternatively selected according to a combination of n (e.g., two) pairs of positive and negative phase signals and provided to output the positive and negative phase signals according to the data stored in the selected memory cell, variable wiring unit provided with signal lines for inter-connecting the variable logical circuits and switching elements for connecting/disconnecting signal lines inter-secting to each other, a wiring connection state storage memory circuit where the states of the switching elements are stored.

Variable logical circuit, semiconductor integrated circuit, and method for manufacturing semiconductor integrated circuit

A test circuit comprised of a microprogram controlled control unit for generating a test pattern (addresses and data) for each memory in accordance with a predetermined algorithm and reading written data, an arithmetic unit, and data determining means for determinating the read data and outputting the result of determination is provided over a semiconductor chip equipped with a memory.

Semiconductor integrated circuit and method of checking memory

A test circuit comprised of a microprogram controlled control unit for generating a test pattern (addresses and data) for each memory in accordance with a predetermined algorithm and reading written data, an arithmetic unit, and data determining means for determining the read data and outputting the result of determination is provided over a semiconductor chip equipped with a memory

Semiconductor integrated circuit and method for testing memory

Magnetic disk unit having anti-impact arrangement

Growing community of inventors

Saitama, Japan

Isao Shimizu