Kabushiki Kaisha Toshiba

Tokyo Ohka Kogyo Co., Ltd.

Sumitomo Osaka Cement Co., Ltd.

Keio University

Fujitsu Corporation

Asahi Kasei Kogyo Kabushiki Kaisha

Waseda University

Isao Sato

Hiroshi Iwahashi

Hiroto Nakai

Kazuhisa Kanazawa

Shigeru Kumagai

Masamichi Asano

Masato Nakajima

Kei Katou

Yasushi Fujii

Toshiharu Takesue

Yasuhiro Takemura

Kazuhiro Mimura

Kazuto Suzuki

Shinichi Kikuchi

Hideo Kato

Kazumasa Wakiya

Tetsuya Osaka

Akira Hashimoto

Yoshio Hagiwara

Shigeru Yokoi

Toshiro Morita

Tokihiko Yokoshima

Tatsuhiko Shibuya

Hiroyuki Iida

Kei Nakata

Norihiko Suzuki

Susumu Takeuchi

Hirooki Aoki

Hideyuki Kametani

Kazuo Maehara

Tomofumi Nishiura

Kenichi Nakano

Osamu Nakajima

An SiO-based film-forming composition giving a protective film which, after impurity diffusion, can be easily stripped off and which has a higher protective effect. The film-forming composition is one for forming a protective film which in the diffusion of an impurity into a silicon wafer, serves to partly prevent the impurity diffusion. This film-forming composition comprises a high-molecular silicon compound and a compound having a protective element which undergoes covalent bonding to the element to be diffused in the impurity diffusion and thereby comes to have eight valence electrons. The protective element is preferably gallium or aluminum when phosphorus is used as the element to be diffused, and is preferably tantalum, niobium, arsenic, or antimony when boron is used as the diffusion element.

Film-forming composition

A 3-D shape measurement apparatus for grasping the state of an object with ease and accuracy is provided. The 3-D shape measurement apparatus includes: a first 3-D sensorhaving a projecting devicefor projecting a light pattern on a target area, and a (first) image capturing apparatusplaced at a first interval dfrom the projecting deviceto capture an image of the target area on which the light pattern is projected; a second 3-D sensorhaving a projecting device, and a (second) image capturing apparatusplaced at a second interval dlonger than the first interval dfrom the projecting deviceto capture an image of the target area on which the light pattern is projected; 3-D information computing meansfor obtaining external shape information on an objectbased on the shift of the pattern on the image acquired with the first 3-D sensor; variation information computing meansfor obtaining variation information on the objectbased on the shift of the pattern on the image acquired with the second 3-D sensor; and information composing meansfor composing the external shape information and the variation information.

Three-dimensional shape-measuring device

A condition analysis apparatus capable of grasping the condition of an object easily and accurately is provided. The condition analysis apparatusincludes a three-dimensional sensorfor measuring sampling-point-moves in the height direction of an objectexisting in a target area at a plurality of sampling points, and area definition meansfor defining an area where a plurality of the sampling-point-moves are in the generally same phase. The thus constructed condition analysis apparatuscan grasp the condition of the objecteasily and accurately. Preferably, the condition analysis apparatusincludes information output meansfor outputting information of an area including the area defined by the area definition means

Condition-analyzing device

A silica-based interlayer insulating layer having a low dielectric constant is formed with SOG material on a substrate, in which a wiring-layer forming space is then formed. If necessary, a UV ray irradiation is performed under an oxidizing atmosphere. A Si&#x2014;OH bond is formed on a surface of the insulating layer. A monomolecular layer film is then adhered to the inner surface of the space, which is then modified to be a catalyst with a solution containing Pd compound. On the catalyst monomolecular layer, a copper-diffusion-resistant film is formed by electroless plating, on which a copper plate is then formed as a wiring layer.

Semiconductor multilayer wiring board and method of forming the same

A network monitoring program automatically sorts fault producing locations on a network. A memory unit stores a fault location determining table containing events indicative of failures of communications via the network, the events being associated with classified elements which can be causes of faults on the network. A communication situation monitoring unit monitors communication situations with respect to other apparatus on the network. A failure detecting unit detects an event indicative of a failure from a communication situation detected by the communication situation monitoring unit. A fault location determining unit determines an element which is responsible for the event detected by the failure detecting unit by referring to the fault location determining table. A fault information output unit outputs fault information representative of a determined result from the fault location determining unit.

Network monitoring program, network monitoring method, and network monitoring apparatus

A material for forming a silica based film which enables the production of a silica based film with a reduced etching rate relative to hydrofluoric acid. This material includes a solid fraction containing a film forming component capable of generating a silica based film, an organic solvent, and water, and the water content of the material, as determined by gas chromatography measurement, is within a range from 0.1 to 50% by weight.

Material for forming silica based film

A method for processing a coating film includes the steps of forming a silica group coating film having a low dielectric constant on a substrate, conducting an etching process to the silica group coating film through a photoresist pattern, and processing the silica group coating film with plasma induced from helium gas. With this, it is possible to prevent the silica group coating film from being damaged when a wet stripping process is conducted to remove the photoresist pattern as a subsequent process, and to maintain the low dielectric constant of the coating film.

Method for processing coating film and method for manufacturing semiconductor element with use of the same method

There is disclosed a semiconductor memory device comprising memory cells (M11 to Mmn) for storing binary data, and first reference cells (DM11 to DMm1) and second reference cells (DM12 to DMm2) corresponding to respective two storage states of the memory cell, to make comparisons between the storage state of the memory cell and the storage states of the both reference cells at first and second sense amplifiers (1, 2) to compare outputs from the both sense amplifiers at the third sense amplifier (3) to thereby detect storage data of the memory cell. Thus, there can be provided a high speed memory device which has a less number of memory cells and of a high integration structure, and which has a little possibility of an erroneous operation in reading.

Semiconductor memory device having redundant memory cells

There is disclosed a semiconductor memory device comprising memory cells (M11 to Mnn) for storing binary data, and first reference cells (DM11 to Dm1) and second reference cells (DM12 to DMm2) corresponding to respective two storage states of the memory cell, to make comparisons between the storage state of the memory cell and the storage states of the both reference cells at first and second sense amplifiers (1, 2) to compare outputs from the both sense amplifiers at the third sense amplifier (3) to thereby detect storage data of the memory cell. Thus, there can be provided a high speed memory device which has a less number of memory cells and of a high integration structure, and which has a little possibility of an erroneous operation in reading.

Semiconductor memory device

In a semiconductor memory device, a first load circuit is coupled with the column lines, first dummy cells are connected to a dummy column line, a second load circuit is connected to the dummy column line, a second dummy cell is connected to the dummy column line, and a sense amplifier senses the data stored in the memory cell in accordance with a potential difference between the column line and the dummy column line. In semiconductor memory devices thus arranged, the second dummy cell is set in an on state normally. The connection of the second dummy cell with the dummy line changes a current flowing to the dummy line at the time of row line switching, thereby to hold back a rise of the reference potential at the time of the row line switching.

Semiconductor memory device with address transition actuated dummy cell

A semiconductor integrated circuit comprises a first input circuit for generating an internal chip enable signal in response to a chip enable signal externally applied; and a second input circuit for supplying to an internal circuit a signal corresponding to a data signal externally applied thereto, the second input circuit containing a gate circuit controlled by an internal chip enable signal. The gate circuit responds to the data signal at a first response speed, and responds to the internal chip enable signal at a second response speed when the semiconductor integrated circuit is changed from the active state to the stand-by state. The second response speed being slower than the first response speed, so as to prevent the semi-conductor integrated circuit from being set into the stand-by state by a false operation of the first input circuit.

Semiconductor integrated circuit with an input buffer circuit for

A nonvolatile semiconductor memory device includes a pulse signal generator for applying a pulse signal to a capacitor, a first diode connected at an anode to the capacitor, a charging circuit for charging the capacitor in a programming mode, a voltage limiter for preventing a potential at the output node from increasing above a predetermined level, memory cells of nonvolatile MOS transistors, a load MOS transistor connected to a high-voltage terminal, a row decoder for selecting a set of memory cells arranged in one row, column gate MOS transistors connected between respective sets of memory cells arranged in one column and the load MOS transistor, a data generator responsive to the voltage at the output node to turn on or off the load MOS transistor, and a column decoder responsive to the voltage at the output node to selectively energize the column gate MOS transistors. It further comprises a second diode connected between the cathode of the first diode and the output node, and a discharging circuit for discharging the cathode of the first diode to a reference voltage level during a time other than a programming mode.

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device includes a memory cell array including a plurality of memory cells each including a nonvolatile transistor, a plurality of row lines each connected to the memory cells arranged on a corresponding row, a plurality of column lines connected to the memory cells arranged on a corresponding column, an address buffer circuit for receiving external address signals at its address input terminal and for outputting internal address signals in response to the received external address signals, column line-select transistors connected to the column lines, a column-decoding circuit for selectively biasing the column line-select transistors, a row-decoding circuit for selectively biasing the row lines, and data-detecting circuit for detecting the potential of the column line selected by the column line-select transistor. The device further includes a control unit generating a control signal for controlling the address buffer circuit so that the internal address signal is set at a predetermined value, to set all the row lines in a non-selected state, thereby setting a column line, selected by the column line-select transistor, at a predetermined potential.

Nonvolatile semiconductor memory device with readout test circuitry

Growing community of inventors

Kawasaki, Japan

Isao Sato