Nec Corporation

Renesas Electronics Corporation

Nec Electronics Corporation

Isao Naritake

Tadahiko Sugibayashi

Hiroyuki Furukawa

Satoshi Utsugi

Tatsuya Matano

Mamoru Fujita

Toshio Takeshima

Tatsunori Murotani

Tetsuya Ootsuki

Provided is a semiconductor integrated circuit including: an anti-fuse element that electrically connects a first node and a first power supply terminal when data is written and electrically disconnect the first node and the first power supply terminal when data is not written; a first switch circuit that is connected between the first node and a first data line applied with a predetermine first voltage, and enters an off state from an on state according to a first control signal; and a detection part that detects write data of the anti-fuse element according to whether a voltage of the first node is substantially the same as the first voltage or substantially the same as a supply voltage of the first power supply terminal when the first switch circuit enters the off state.

One-time programmable cell circuit, semiconductor integrated circuit including the same, and data judging method thereof

An anti-fuse memory cell includes: a first transistor connected with a word line and configured to output a second voltage based on a first voltage supplied to the word line in a write mode; a second transistor connected with a bit line, and configured to output a third voltage supplied to the bit line when the second voltage is supplied to a gate of the second transistor in the write mode; and an anti-fuse element connected to a ground line, and having an insulator film. The insulator film is set to a conductive state with the third voltage supplied from the second transistor.

Anti-fuse memory cell and semiconductor memory device

A semiconductor integrated circuit device includes: a first bias generating circuit, a second bias generating circuit and a control circuit. The first bias generating circuit generates a first substrate bias voltage of a P-channel transistor. The second bias generating circuit generates a second substrate bias voltage of N-channel transistor. The control circuit controls the first bias generating circuit and the second bias generating circuit independently on the basis of operating states of circuits to which the first substrate bias voltage and the second substrate bias voltage are applied.

Semiconductor integrated circuit device and substrate bias controlling method

A semiconductor integrated circuit, includes a first macro and a second macro. The first macro outputs a data signal. The second macro inputs the data signal. The first macro fixes the data signal at a non-high level state that is not a high level in response to a control signal.

Semiconductor integrated circuit including a plurality of macros that can be operated although their operational voltages are different from each other

A semiconductor memory device is provided with an MPU, a secondary cache and a TAG memory mounted on a chip. Registers are provided for a plurality of test data buses connected parallel to a plurality of data buses from the MPU to the secondary cache or the TAG memory. The registers and the plurality of data buses of the MPU are changed with switches so as to be connected with a bonding pad which is a part of an external terminal for the MPU. With this arrangement, the semiconductor memory device can connect with a tester for a DRAM part test via the bonding pad.

Semiconductor memory device

A dynamic semiconductor memory device for writing/reading out data in/from a memory cell via a write/read circuit determined by a word line selected by a row address and a bit line selected by a column address, and temporally holding burst-written/read data by a data latch arranged on a data line connected to the write/read circuit includes an address transition detection circuit and a read-after-write circuit. The address transition detection circuit detects an address change to generate an operation start instruction signal, and starts a write/read cycle in accordance with the operation start instruction signal. The read-after-write circuit detects a change from a write mode to a read mode to generate a read-after-write instruction signal. When the read-after-write instruction signal is generated, data held by the write/read circuit is transferred to the data latch, and when the data is held by the data latch and read is done for the same row address, the data held by the data latch is read out and output. A semiconductor memory device manufacturing method is also disclosed.

Semiconductor memory based on address transitions

A semiconductor memory device such as a DRAM device in which, in each write or read cycle, a plurality bits of data are written to or read from memory cells as a burst. The semiconductor memory device includes: a plurality of write/read circuits for reading data from selected memory cells to data lines and writing data from the data lines to selected memory cells; a column selector for distributing data from an input/output line to the data lines, and outputting data from the data lines to the input/output line; and a plurality of data latches inserted into data line circuit portions between the column selector and the write/read circuits, for temporarily storing data to be written to or read from the memory cells as a burst. In a write cycle, after data stored in the latches is written into memory cells and after elapsing a predetermined time period required for a precharge operation of the bit lines, the next write cycle is started. In a read cycle, after data is read out from memory cells into the data latches and after performing a precharge operation of the bit lines, the next read cycle is started.

Semiconductor memory device which continuously performs read/write operations with short access time

In a dynamic type semiconductor memory device having a classified bit line structure, a feedback capacitor is provided between sub-bit lines and main bit lines of a sub-sense amplifier. A voltage difference read out on the sub-bit lines is transferred to the main bit lines, the read out voltage difference is amplified by a main sense amplifier, and data of superordinate bits is read out. At the same time, the data on said main bit lines is feed-backed to the sub-bit lines through the capacitor. Thereafter, a reading operation from the sub-bit lines to the main bit lines is performed again, thereby enabling a reading operation for data of subordinate bits. Thus, in a dynamic type semiconductor memory device having a conventional memory cell structure, data for two bits can be stored in one memory cell.

DRAM having each memory cell storing plural bit data

There is provided a dynamic type semiconductor memory device including (a) a first hierarchized complementary bit line, (b) a second hierarchized complementary bit line, (c) a first sense-amplifier electrically connected to the first bit line, (d) at least one second sense-amplifier electrically connected to both the first bit line and the second bit line, (e) a capacitor located between the first and second bit lines for each of second sense-amplifiers, and (f) a transfer gate arranged in series with the capacity between the first and second bit lines. The above-mentioned dynamic type semiconductor memory device makes it possible to store two-bit data in a single memory cell by employing a memory cell comprised of one transistor and one capacitor, without the use of a conventional memory cell having two transistors and one capacitor. Hence, the dynamic type semiconductor memory device ensures a significant reduction in a chip area.

Dynamic type semiconductor memory device having function of compensating

In a region of a transfer gate provided in a central portion of multilevel writing bit lines, noise in adjacent bit lines at the time of re-writing is counteracted by reversing the order of complementary bit line pair every other pair. With this, in a multilevel dynamic type semiconductor memory device in which one sense amplifier commonly includes a plurality of bit lines and some of the bit lines are selectively activated in a time-dividing manner, the influence of noise between the adjacent bit lines can be deleted.

Multi-value dynamic semiconductor memory device having twisted bit line

A semiconductor dynamic random access memory device serially reads out data bits from and serially writes data bits into memory cells through a long burst cycle, and the data bits are transferred between a read/write data bus to data latch circuits, between the data latch circuits and the main/sub sense amplifiers and the main/sub sense amplifiers and the sub-bit line pairs; while the data bits are being stepwise transferred between the memory cells and the read/write data bus, an internal timing controller not only provides activation timings and deactivation timings to the main-sub sense amplifiers and transfer gate arrays but also the starting point and the end point of the long burst cycle so that the semiconductor dynamic random access memory device is fabricated on a relatively small semiconductor chip.

Semiconductor memory device having internal timing generator shared

In a dynamic type semiconductor memory device having a classified bit line structure, a feedback capacitor is provided between sub-bit lines and main bit lines of a sub-sense amplifier. A voltage difference read out on the sub-bit lines is transferred to the main bit lines, the read out voltage difference is amplified by a main sense amplifier, and data of superordinate bits is read out. At the same time, the data on said main bit lines is fed back to the sub-bit lines through the capacitor. Thereafter, a reading operation from the sub-bit lines to the main bit lines is performed again, thereby enabling a reading operation for data of subordinate bits. Thus, in a dynamic type semiconductor memory device having a conventional memory cell structure, data for two bits can be stored in one memory cell.

DRAM having memory cells each using one transfer gate and one capacitor

A semiconductor dynamic random access memory device has memory cells each storing a piece of multiple-valued data equivalent to two-bit binary data in the form of electric charge, and sub-bit line pairs selectively connected to the memory cells use parasitic capacitors coupled thereto as charge accumulators weighted by two, wherein the piece of multiple-valued data transferred from the sub-bit line pair to a main bit line pair supplies a first potential level to one of the charge accumulators assigned to the most significant bit and a second potential level to another of the charge accumulators assigned to the least significant bit, and dummy cells are selectively coupled to the charge accumulators so as to make storage capacitance coupled to the charge accumulator assigned to the most significant bit twice as large as the storage capacitance coupled to the charge accumulator assigned to the least significant bit, thereby eliminating electrical influence of the storage capacitor of the selected memory cell from a restore level.

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Tokyo, Japan

Isao Naritake