Matsushita Electric Industrial Co., Ltd.

Socionext Inc.

Isao Motegi

Masanobu Hirose

Hiroki Shinde

Toshihiro Nakamura

Eiji Nagata

Hiroki Tomoshige

Taro Fukunaga

Noriyuki Shimazu

Masaki Ishino

Noriko Oosuka

A semiconductor chip having a core region and an I/O region which surrounds the core region is provided with a plurality of external connection pads connected to I/O cells. The plurality of external connection pads include a first pad group comprised of the external connection pads connected to the same node, and a second pad group comprised of the external connection pads connected to respective different nodes. In first and second pad groups, the external connection pads are arranged in an X direction along an external side of the semiconductor chip, and a pad arrangement pitch in the first pad group is smaller than that in the second pad group.

Semiconductor chip and semiconductor device provided with same

In a standard cell synthesizing step, a net list is synthesized from an RTL description, and an instance name list is formed which contrasts a register description portion with an instance name contained in the net list; in a simulation step, an operation simulation written by the RTL description is carried out; the toggle information among registers which is extracted in the simulation stepis recorded in a toggle storing step, a flip-flop-to-flip-flop toggle information database is constructed in which the recorded toggle information corresponds to a flip-flop-to-flip-flop instance name obtained from the instance name list in a mapping step; and in an electric power optimizing step, a physical designing operation for reducing power consumption is optimized by employing the net list, the flip-flop-to-flip-flop toggle information database, and a timing restriction.

Low power consumption designing method of semiconductor integrated circuit

An inter-block interface circuit which effectively prevents occurrences of inconveniences (for example, such that a shoot-through current flows due to unsteady potential in wiring) caused by switching off a power supply of a block, using simple circuitry, in LSI such that signals are communicated between the blocks and the power supplies of the blocks are interrupted independently. In the circuit, gate circuitsandare respectively provided in blocksandthat communicate signals with one another, and interface control circuitdynamically controls respective input levels of gate circuitsand. In other words, the circuitfixes an input level of gate circuitorin a block whose power supply is ON to 'L', and thereby compulsively fixes an output level of the gate circuit to 'L'.

Inter-block interface circuit and system LSI

An apparatus for obtaining correlation by despreading a spread symbol with a spreading code is provided with a symbol storage section for storing symbol and a plurality of correlation calculators each of which executes a correlation calculation to obtain correlation by despreading the symbol data with a spreading code. The apparatus switches a spreading code to be provided to each of the plurality of correlation calculators individually so that each of the plurality of correlation calculators executes correlation calculation with a respective different spreading code and holds a same spreading code until correlation calculations of a plurality of symbols are finished.

Correlation detection apparatus and CDMA receiving apparatus

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Yokohama, Japan

Isao Motegi