Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Isao Miyanaga

Takayuki Yamada

Shin Hashimoto

Kyoji Yamashita

Hisashi Ogawa

Mizuki Segawa

Takashi Nakabayashi

Takaaki Ukeda

Takashi Uehara

Toshiki Yabu

Masatoshi Arai

Michikazu Matsumoto

Yasushi Okuda

Toshio Yamada

Atsushi Hori

Atsushi Fujiwara

Kazumi Kurimoto

Masanori Fukumoto

Yoshirou Nakata

Yuka Terai

Mitsuru Sekiguchi

Shuji Hirao

Yukiharu Uraoka

Kenzou Hatada

Kazuichiro Itonaga

Akihiro Yamamoto

Shinji Odanaka

Hiroaki Nakaoka

Yoshiro Nakata

Yoshinao Harada

Yoshihiro Mori

Koji Eriguchi

Atsuhiro Kajiya

Akira Hiroki

Kentaro Nakanishi

Masayuki Kamei

A semiconductor device includes a first MIS transistor of a non-salicide structure and a second MIS transistor of a salicide structure which are both formed on a substrate of silicon. The first MIS transistor includes a first gate electrode of silicon, first sidewalls, a first source and drain, and plasma reaction films grown in a plasma atmosphere to cover the top surfaces of the first gate electrode and first source and drain, wherein the plasma reaction film prevents silicide formation on the first MIS transistor.

Semiconductor device having silicide transistors and non-silicide transistors formed on the same substrate and method for fabricating the same

In a semiconductor device according to the present invention, the power source voltage Vddof a core transistor Trthe power source voltage Vddof an I/O transistor Trand the power source voltage Vddof an I/O transistor Trsatisfy Vdd&#x3c;Vdd&#x3c;VddIn a method for fabricating the semiconductor device, each of the respective gate insulating films of the I/O transistors Trand Tris formed in the same step to have the same thickness. Each of the respective SD extension regions of the core transistor Trand the I/O transistor Tris formed at the same dose.

Semiconductor device and method for fabricating the same

An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

Semiconductor device and method of manufacturing the same

After forming a gate electrode on a semiconductor substrate, ion implantation is performed on the semiconductor substrate by using the gate electrode as a mask to form low concentration impurity regions, and thereafter first sidewall insulating films are formed on the side surfaces of the gate electrode. Next, by using the gate electrode and the first sidewall insulating films as a mask, ion implantation is performed on the semiconductor substrate to form high concentration impurity regions, and thereafter second sidewall insulating films are formed on the side surfaces of the first sidewall insulating films. After that, by using each sidewall insulating film as a mask, metal silicide layers are selectively formed on each surface of the semiconductor substrate and the gate electrode.

Semiconductor device and manufacturing method thereof

With keeping an atmosphere including oxygen within a chamber and with a wafer kept at a low temperature, plasma generated within the chamber is biased toward the wafer, and the wafer is subjected to the plasma. A semiconductor layer exposed on the wafer is oxidized into an oxide film. Thus, an oxide film can be formed even at room temperature differently from thermal oxidation. This oxidation is applicable to recovery of an implantation protection insulating film having been etched in cleaning a photoresist film, relaxation of a step formed between polysilicon films, relaxation of a step formed within a trench and the like. Also, before removing a photoresist film used for forming a gate electrode including a metal, a contamination protection film can be formed by this oxidation with the photoresist film kept.

Method of forming insulating film and method of fabricating semiconductor device including plasma bias for forming a second insulating film

A memory cell transistor and a trench capacitor are provided in a memory region, and both transistors of CMOS are provided in a logic circuit region. There are provided a bit line contactand a bit lineextending on an inter-level dielectric. In a memory cell transistor, a source diffusion layeris covered with two dielectric sidewallsandin the memory cell transistor so that no silicide layer is formed on the source diffusion layer. A plate contactis provided to pass through the inter-level dielectricand connect a shield lineto a plate electrode. The shield lineis arranged in the same interconnect layer as the bit line

Semiconductor device

With keeping an atmosphere including oxygen within a chamber and with a wafer kept at a low temperature, plasma generated within the chamber is biased toward the wafer, and the wafer is subjected to the plasma. A semiconductor layer exposed on the wafer is oxidized into an oxide film. Thus, an oxide film can be formed even at room temperature differently from thermal oxidation. This oxidation is applicable to recovery of an implantation protection insulating film having been etched in cleaning a photoresist film, relaxation of a step formed between polysilicon films, relaxation of a step formed within trench and the like. Also, before removing a photoresist film used for forming a gate electrode including a metal, a contamination protection film can be formed by this oxidation with the photoresist film kept.

Method of forming insulating film and method of fabricating semiconductor device

A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.

Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method

Semiconductor device which reduces the minimum distance requirements between active areas

Semiconductor wafer package, method and apparatus for connecting testing

A 12.5-MHz signal is applied from outside a semiconductor integrated circuit (SIC) device to a signal input terminal of that SIC device. A frequency multiplying circuit is fed that 12.5-MHz signal from the input terminal, and delivers a reference signal whose frequency is a multiple of the frequency of the signal received (i.e., 100 MHz), to a semiconductor memory and to a self-test circuit. The self-test circuit provides a test signal in synchronism with that 100-MHz reference signal to the semiconductor memory for testing for the presence or absence of a failure. All elements of the semiconductor memory are tested by the self-test circuit for a failure. If the self-test circuit finds a semiconductor memory element that fails to work properly, it provides a signal indicative of such failure to a failure counting circuit. This failure counting circuit counts the number of times the self-test circuit provides such a signal.

Semiconductor integrated circuit device having failure detection

Growing community of inventors

Nara, Japan

Isao Miyanaga