Kabushiki Kaisha Toshiba

Nec Corporation

Nec Electronics Corporation

Sumitomo Bakelite Company Limited

Renesas Electronics Corporation

Isao Katayama

Kohji Kanamori

Noriaki Kodama

Teiichirou Nishizaka

Yoshihiro Matsuura

Kaoru Ishihara

Naruaki Minenaga

Chihiro Oshita

Yasushi Harada

Masatoshi Iji

Yukihiro Kiuchi

Katsushi Terajima

Yasuo Matsui

Ken Oota

A CPU includes an address decoder that controls input of data from a JTAG I/F and output of data to the JTAG I/F, an authentication unit that performs predetermined authentication processing using an entered password and a predetermined key and, if the authentication is successful, output a predetermined authentication signal, and a selector that controls output of data to be outputted to JTAG I/F according to presence or absence of the predetermined authentication signal.

Processor and semiconductor device

According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.

Semiconductor storage device, semiconductor device, and manufacturing method therefor

An epoxy resin composition which can be used as a semiconductor encapsulating resin and in which the improvement of flame retardancy can be attained by suitably adapting a crosslinked structure itself of a cured article without using any flame retardant material and without particularly highly filling an inorganic filler. The epoxy resin composition includes an epoxy resin (A), a phenolic resin (B), an inorganic filler (C) and a curing accelerator (D), wherein a flexural modulus E (kgf/mm) at 240&#xb1;20% C of a cured article obtained by curing the composition is a value satisfying 0.015 W+4.1&#x2266;E&#x2266;0.27 W+21.8 in the case of 30&#x2266;W&#x3c;60, or a value satisfying 0.30 W&#x2212;13&#x2266;E&#x2266;3.7 W&#x2212;184 in the case of 60&#x2266;W&#x2266;95 wherein W (wt %) is a content of the inorganic filler (C) in the cured article. The cured article of this composition forms a foamed layer during thermal decomposition or at ignition to exert flame retardancy.

Composition of biphenyl epoxy resin, phenolbiphenylaralkyl resin and filler

Semiconductor device of a charge storage type

A computer readable medium encoded with a hardware description language describing a virtual component for an integrated circuit design, the virtual component comprising a virtual component body having at least one circuit function and a verification-supporting circuit detachably connected to the virtual component body. The verification-supporting circuit may include a verification-output terminal described by the hardware description language. The verification-output terminal is configured to output a signal indicating an operation state inside of the virtual component body, and is detachably connected to the virtual component body so as not to affect the operation of the virtual component body even when the connection of the verification-output terminal with the virtual component body is cut.

Virtual component having a detachable verification-supporting circuit, a method of verifying the same, and a method of manufacturing an integrated circuit

Flame-retardant epoxy resin composition and semiconductor device made using the same

In a central processing unit, caching is carried out for an instruction cache tag memory, so that, without making modifications to a conventional instruction cache controller, the number of times of access to the instruction cache tag memory, which consumes a large amount of electric power, is reduced, and low electric power consumption is attained.

Instruction cache and microprocessor

A central processing unit schedules the start time of a following special process based on the progress status of a preceding special process being executed in an auxiliary processing unit and the processing time and the end time of the following special process.

Data processing system and scheduling method

An interrupt program selection system which is provided with a central processing unit executing various types of control programs stored in a storage unit and which accepts an interrupt processing request from an external unit and selects from the storage unit an interrupt program corresponding to the accepted request comprises an interrupt request controller, a conversion table, and a jump code generating module. The interrupt request controller selects a highest-priority processing request from a plurality of interrupt processing requests. The conversion table contains start addresses of a plurality of interrupt programs corresponding to a plurality of interrupt processing requests. The jump code generating module generates a jump code which may be executed directly by the central processing unit as an instruction based on the start address of the interrupt program corresponding to the accepted interrupt processing request, and places the generated code in a memory space in the storage unit.

Jump code generator, interrupt program selection system, interruption

Growing community of inventors

Kanagawa, Japan

Isao Katayama