Fujitsu Corporation

Fujitsu Microelectronics Limited

Fujitsu Vlsi Limited

Fujitsu Semiconductor Limited

Fujutsu Limited

Isao Fukushi

Shoichiro Kawashima

Keizo Morita

Tomoharu Awaya

Takashi Ozawa

Yasuhiko Maki

Hideaki Isogai

Yoshiaki Kaneko

Yasuhiro Ishii

Shingo Hagiwara

Amane Inoue

Akihito Kumagai

Takahisa Muroi

Mitsuhiro Ogai

A regular capacitor is saturated by an electric charge of a regular memory cell holding a high logic level and is not saturated by an electric charge from the regular memory cell holding a low logic level. A reference capacitor is saturated by the electric charge from a reference memory cell holding the high logic level. A differential sense amplifier differentially amplifies a difference between a regular read voltage read from the regular capacitor and a voltage which is lower by a first voltage than a reference read voltage being a saturation voltage read from the reference capacitor, and generates logic of data held in the memory cell. Accordingly, a difference between the reference voltage and the read voltage corresponding to the low logic level can be made relatively large. As a result, it is possible to improve a read margin.

Semiconductor memory

A power supply voltage detection circuit is provided including: a first switch to connect between a power supply voltage terminal and a first terminal according to a power supply voltage detection signal and an external signal; a second switch to connect between a reference potential terminal and a second terminal according to the power supply voltage detection signal and the external signal; a first resistance connected between the second terminal and the power supply voltage terminal; and a third switch connecting between the first terminal and the reference potential terminal according to a voltage of the second terminal; and an output circuit outputting the power supply voltage detection signal based on a signal from the first terminal.

Power supply voltage detection circuit

A nonvolatile decision memory unit stores decision data indicating whether data stored in the normal memory cells is true or false. An inversion control circuit sets the inverting signal to a valid level with a predetermined probability. A write circuit writes data having logic which is inverse logic of data to be rewritten to the normal memory cells and writes decision data indicating false to the decision memory unit when the inverting signal indicates a valid level. Since inverse data is rewritten at a predetermined frequency, an imprint is prevented when a read operation is executed repetitively. Moreover, since frequent repeating of reverse polarization of the ferroelectric capacitor due to a rewrite operation is prevented, deterioration of the ferroelectric capacitor due to reverse polarization is minimized. Thus, occurrence of the imprint and deterioration of characteristics in the ferroelectric capacitor is prevented, and the reliability of the ferroelectric memory is improved.

Ferroelectric memory and operating method of same

A bit line is connected to a charge storing circuit through a charge transferring circuit. A control circuit controls charge transferability of the charge transferring circuit according to a change in the voltage of the bit line resulting from a charge read out from a memory cell. A leakage controlling circuit lowers the charge transferability of the charge transferring circuit in a read operation temporarily before the charge is read out to the bit line. The leakage controlling circuit makes it possible to avoid charge transfer between the charge storing circuit and the bit line before data is read from the memory cell. The charge storing circuit can thus generate a read voltage sufficient for a read circuit to operate with, in accordance with the logical value of the data stored in the memory cell.

When an address storing/comparing circuit stores no address identical to an external input address in read operation, in a main memory read data is written back to a data storing area after data read therefrom, and data indicating a sum of a predetermined value and a value of the read data is written to a history storing area after data read therefrom. In a sub memory, after data read from a history storing area, data read from the data storing area of the main memory is written to a data storing area and the data indicating the sum of the predetermined value and the value of the data read from the history storing area of the main memory is written to the history storing area, when the value of the data read from the history storing area of the main memory is larger than that of the sub memory.

Non-volatile semiconductor memory

A ferroelectric memory has a plurality of memory cells respectively having a cell transistor and ferroelectric capacitor whose one terminal is connected with the cell transistor, a plurality of word lines respectively connected with said cell transistor, a plurality of plate lines connected with the other terminal of said ferroelectric capacitor and intersecting with said word lines, a plurality of local bit lines connected with said cell transistors, and a global bit line that is selectively connected with local bit lines. Furthermore, the ferroelectric memory has a sensing amplifier unit that detects the amount of charging of the local bit lines from said memory cells while maintaining the potential of the local bit lines at a potential equivalent to the non-selected plate lines, during reading.

A semiconductor memory device includes a memory cell, a signal line on which a potential responsive to data read from the memory cell appears, a potential detecting circuit which outputs a detection signal in response to detecting that the potential on the signal line exceeds a predetermined potential, and a sense amplifier which starts amplifying the potential on the signal line in response to the detection signal.

Semiconductor memory device with proper sensing timing

A semiconductor memory device includes a memory cell, and a dynamic latch type sense amplifier including transistors that form not only a dynamic latch circuit which holds or releases data but also charge transfer gates via which charges are applied to or received from bit lines. Data is read from the cell connected to the bit lines at a same time as a precharging operation on the bit lines.

Semiconductor memory device

Semiconductor memory having improved sense amplifier

A semiconductor memory device comprises a memory cell array, a column decoding unit supplied with first address data addressing a column of the memory cells for producing a column selection signal, a column switch unit supplied with the column selection signal for connecting a selected bit line to a corresponding common bit line, a row decoding unit supplied with second address data addressing a row of the memory cells for producing a word line selection signal, a plurality of sensing circuits each having an input terminal connected to a common bit line for detecting a voltage appearing on the common bit line, a plurality of writing circuits each connected a corresponding common bit line for writing the data into the addressed memory cell by causing a change in the voltage on the common bit line, and a disconnection circuit between the sensing circuit and the common bit line in each column of the memory cells wherein the disconnection circuit is controlled by the writing circuit such that the sensing circuit is selectively disconnected from the common bit line when the writing circuit writes the data into the memory cell.

Semiconductor memory device having sense amplifier protection

A multi-port semiconductor memory includes a memory cell array having a plurality of memory cells (10), a plurality of columns and rows, a write/read system, and at least one read system having sense amplifiers, each of the columns having a pair of data lines. Each of the sense amplifiers has first and second terminals connected to the pair of data lines and senses a voltage difference between the first and second terminals. The multi-port semiconductor memory also includes an address coincidence detection circuit which generates a control signal when a first address provided for writing write data into the memory cell array by the write/read system coincides with a second address provided for reading the write data by the read system. Further, the multi-port semiconductor memory includes a read control circuit which is provided in each of the sense amplifiers and which connects the first and second terminals of a corresponding one of the sense amplifies to the pair of data lines when the address coincidence detection circuit generates no control signal and which sets one of the first and second terminals to a predetermined voltage on the basis of the content of the write data while the other one of the first and second terminals is connected to a corresponding one of the pair of data lines.

Multi-port semiconductor memory

Emitter follower circuit with MOSFET

A semiconductor memory device including a plurality of level converters, each of the level converters including a bridge circuit constituted by four MOS transistors having one type of conductivity, gates of one pair of four transistors opposing each other receiving a first signal and gates of the other pair of four transistors opposing each other receiving a signal complementary to the first signal; a pair of complementary MOS inverter circuits to which a second signal and a signal complementary to the second signal are input, respectively, the outputs of the pair of inverter circuits being connected to a first pair of connecting points positioned alternately in the bridge circuit, respectively; and a flip-flop circuit connected between a second pair of connecting points positioned alternately in the bridge circuit, to thereby output a third signal and a signal complementary to the third signal from the second pair of connecting points, resepctively.

Semiconductor memory device having level converters

A bipolar-complementary metal oxide semiconductor circuit includes a p-channel MOS transistor, and an n-channel MOS transistor, first and second bipolar transistors. A base of the first bipolar transistor is connected to a negative power source through the n-channel MOS transistor. A diode is connected to the base and emitter of the first bipolar transistor. The diode functions to prevent a reverse-biased voltage exceeding a base-emitter breakdown voltage from being applied between the base and emitter of the first bipolar transistor.

Growing community of inventors

Kawasaki, Japan

Isao Fukushi