Fujitsu Corporation

Isao Azuma

Naozumi Aoki

Miyuki Ishida

An electronic circuit device able to diagnose a status-holding circuit by scanning, the device comprising a first plurality of integrated circuits each including a serial scan circuit for receiving serial data, generating an address value of a target status-holding circuit as parallel data from the received serial data, and selecting the target status-holding circuit having the generated address value, and a second plurality of integrated circuits each including a parallel scan circuit for receiving an address value of a target status-holding circuit as parallel data and selecting the target status-holding circuit having the received address value. Address information received as serial data being used for generating parallel address information, and address information received as parallel data being used for generating serial address information.

Electronic circuit device able to diagnose status-holding circuits by

A buffer storage control system is incorporated in a multiprocessor and includes therein operand side buffer storages and instruction fetch side buffer storages. Under control of the system, a store operation is achieved with the use of an identification flag, which indicates that the related address invalidation is to be effected at the operand side or the instruction fetch side, while a fetch operation is achieved with the use of the identification flag which indicates that the related store address is to be recorded in the operand side buffer memory (TAG) or the instruction fetch side buffer memory (TAG).

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Yokohama, Japan

Isao Azuma