Tokyo Shibaura Denki Kabushiki Kaisha

Tokyo Shibaura Electric Co., Ltd.

Kabushiki Kaisha Toshiba

The President of the Agency of Industrial Science and Technology

Isamu Yamazaki

Tsuneo Kinoshita

Fumitaka Sato

A method of automated theorem proving for information processing which can be highly efficient, irrespective of the set of clauses to be dealt with. The method includes the steps of: transforming the statement and the set of knowledge into expressions in terms of elements of a module; constructing a linear equation with the elements of the module as coefficients and the elements of a ring of scalars of the module as unknowns; checking the existence of a non-negative solution to the linear equation; and determining that the statement is provable when the non-negative solution exist, and not provable otherwise.

Method and apparatus of automated theorem proving for information

A matrix logic circuit network comprises a great number of interconnected logic gates. Input and output lines of the logic gates are arranged in the matrix array. By rearranging the input and output lines of the matrix in accordance with a sort algorithm, direct connection points of the input and output lines to which the same signals are allotted and connecting elements forming logic gates located at given intersections of the input and output lines are arranged within a diagonal area with a limited width, which extends along a diagonal line of the matrix.

Matrix logic circuit network suitable for large-scale integration

The vector processor of the present invention is designed to have a first function for classifying, generating and storing in advance a separate index set by judging the attribute of specified data and a second function for continuously performing operand access only for the index value belonging to the specified index set out of the index sets generated by the first function, thus avoiding the deterioration of the efficiency of pipeline processing even when the calculation of array data has different operation content according to the attributes of the specified data. Accordingly it can perform continuous calculation of a plurality of different conditioned expressions at high speed by arranging it to operate the first and the second functions concurrently with the value resulting from the operation by the second function being used by the first function as a data for discriminating the attribute of the data.

Index limited continuous operation vector processor

In a one-chip high density arithmetic control unit capable of prefetching user's instructions from main memory, an arithmetic logic unit (ALU) subtracts the contents of a location counter holding the address of the next instruction to be executed, from the contents of a memory address register holding an address into which data will be written. The difference is fed through the gates connected to the ALU for determining whether or not prefetched instructions will have to be refetched. An address matching mechanism provided outside the one-chip arithmetic control unit includes a comparator for comparing memory addresses to a preset execution stop address. The output signal of the comparator is stored in a memory section which is provided to correspond to the prefetched instruction buffer, and when an instruction stored in the prefetched instruction buffer is transferred to an instruction register, the signal stored in the corresponding memory section is also read out and used to determine whether to stop execution. Further, whenever access is made to main memory a signal indicating whether the access is legal is externally generated and may be stored in a second memory section. Like the address matching signal, this signal is read out when the corresponding instruction from the prefeteched instruction buffer is transferred to the instruction register. An illegal address interruption is produced when this signal indicates that the address was illegal.

Information-processing system having a single chip arithmetic control

A shift circuit comprises a plurality of stages of data selectors, a first data selector, a second data selector and a temporary register. The data selectors shift an n-bit input data by m bits which are specified by a shifting amount data and produces a first output data or a second output data. The first and second data selectors selectively output the first and second output data in accordance with shift direction. The temporary register comprises n bits for storing a data which is not selected by said first or second data selector.

Shift circuit having a plurality of cascade-connected data selectors

In an information processing system in which an arithmetic control unit is formed on one chip by very large scale integration and is connected to external devices by a common bus, microinstructions from an externally-connected control memory, memory information output from an external main memory and information output from I/O devices, can be received by the arithmetic control unit on the common bus. An external setting signal for selecting whether the instruction system of the arithmetic control unit is to be enabled or disabled is input to the arithmetic control unit on the common bus simultaneously with the fetching of a microinstruction. A bus width setting signal from an I/O device is also input to the arithmetic control unit on the common bus simultaneously with the fetching of a microinstruction, and the CPU determines whether the data width of an I/O device is 8 bits or 16 bits. An interruption signal from an I/O device and a signal indicating an abnormal condition of a power source, for example, may be input to the arithmetic control unit from external devices on the common bus as part of a group of external signals occupying only a portion of the common bus simultaneously with the fetching of a microinstruction on the remaining portion of the common bus. When exchanging a plurality of kinds of data with different phases between the arithmetic control unit and external devices on the common bus, an external status signal unique to each phase is input to the arithmetic control unit on a common signal line in synchronism with each phase.

Information processing system including a one-chip arithmetic control

A computer system in which the configuration of a plurality of information processing modules, which are provided in at least first and second configuration points, may be automatically monitored and supervised, comprises a plurality of switching modules provided in a third configuration point, each switching module having a configuration point number and each of the information processing modules having an identification number; and a configuration monitoring center for at least monitoring the connecting conditions between the switching modules and the configuration monitoring center for supervision of the computer system. Timing signals are delivered from the configuration monitoring center to inquire about conditions in the information processing modules and switching modules. Status lines are provided for delivering response signals representing the conditions and identification numbers of the information processing modules and configuration point numbers of the switching modules in the first and second configuration points and third configuration point to the configuration monitoring center and status distribution lines are provided for transferring the response signals from the information processing modules in the first and second configuration points to the switching modules in the third configuration point. The switching modules in the third configuration point each include a response generator which is responsive to the timing signals for delivering a combination of response signals from the information processing modules in the first and second configuration points to the configuration monitoring center by way of the status lines.

Computer system with a configuration monitor

A microprogrammed control system comprises: a memory for storing a microprogram programmed with microinstructions; a memory for storing microinstructions for branching microinstruction; an address register for storing the address of the microinstruction to be next executed; and a microinstruction register for storing the microinstruction to be executed. The program operation of the microprogrammed control system depends on whether the micro-instruction stored in the microinstruction register is the branching one or not. In the case of non-branching microinstruction, the operation of ordinary microinstructions is executed. In the case of branching microinstruction, a special operation is executed for making the operation of the branching microinstruction equivalent to that of the ordinary microinstruction.

Microprogrammed control system

A microprogram controlled system to which is applied the vertical type microprogramming technique. Microinstructions fetched from a control stage are decoded in a control decoder, which controls gates of registers in a central processor to execute the microinstructions. The microinstructions include an extension field in the format to modify the functions thereof.

Microprogram controlled system

A microprogrammed LSI microprocessor comprises a read only memory (ROM) for storing therein microprograms and a decode table for the operation code of macroinstructions, and an arithmetic logic control section constructed into a one package of LSI circuit. The arithmetic logic control section is constructed into a circuit arrangement which, on the assumption that the operation code of macroinstructions be an address, sets the starting address of a corresponding macroinstruction read from the ROM in a location counter, reads from the ROM a microinstruction corresponding to the starting address set in the location counter to set this microinstruction in a microinstruction register, and arithmetically executes the microinstruction stored in the microinstruction register.

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Kawasaki, Japan

Isamu Yamazaki