Ricoh Company, Ltd.

Isamu Moriwaki

Toshihiro Shigemori

Hiroyuki Kiguchi

Keitaro Ado

A coding circuit that includes a buffer manager and a coding block is provided for generating product codes for parity checks as error correction code and adding the product codes to digital data to be recorded in a record medium.

Coding circuit for recording data on DVD disk

A receiver for a differential signal transmitted over a serial interface includes a squelch detector, a differential amplifier, a start pattern detector, an end pattern detector, and a controller. The squelch detector is configured to output a squelch signal when determining that the differential signal is present on the serial interface. The differential amplifier is configured to extract binary data from the differential signal. The start pattern detector is configured to indicate a first state when detecting a given start pattern in the binary data. The end pattern detector is configured to indicate a second state when detecting a given end pattern in the binary data. The controller is configured to activate the start pattern detector in response to the squelch signal. The controller is configured to validate the differential signal in the first state. The controller is configured to end receiving the differential signal in the second state.

Circuit and method for differential signaling receiver

A clock and data recovery circuit that includes a unit to output N-phase clocks each of which has a phase shifted from the others by a time Tobtained by dividing a clock period Pby N, a unit to obtain sampling data serially transferred every time T, a unit to convert the sampling data into first N-bit parallel data every period P, a unit to convert the first N-bit parallel data into second N-bit parallel data indicating a change point in the sampling data, and a unit to use the second N-bit parallel data as input of phase information and output third N-bit parallel data indicating substantially a center position of the change point. N is an integer greater than 2 and data of the first N-bit parallel data at a position equal to the position indicated by the third N-bit parallel data is determined to be recovered data.

Clock and data recovery circuit and communications apparatus including the clock and data recovery circuit

An optical disk apparatus includes a binarizing circuit part for outputting a reference digital signal, and a digital PLL circuit part for outputting a write timing signal based on the reference digital signal, the write timing signal indicating a timing synchronizing with a digital clock signal having a predetermined frequency. The digital PLL circuit part includes an edge detection circuit part for detecting a rise edge and a fall edge of the reference digital signal in time resolution units in which a single period of a reference clock signal is divided into N (N where is no less than 2) intervals and outputting an edge detection signal for each the single period in accordance with the detection result, a digital clock data generating part for generating digital clock data in accordance with a phase difference indicated in an input phase difference signal in each the single period, and a phase difference detection circuit part for detecting a phase difference between the reference digital clock signal and the digital clock signal and outputting the phase difference signal indicating the detected phase difference.

Digital PLL circuit and optical disk apparatus having digital PLL circuit

A semiconductor device includes a current-driven differential driver and a control circuit. The current-driven differential driver is configured to generate a pair of signals having levels relative to each other from a serial signal input therein and output a current from a current source included therein through an output node according to each of the signals. The control circuit controls the current-driven differential driver to pass the current from the current source as a throwaway current therein during a second predetermined time after an input of the serial signal stops and to block the throwaway current after the second predetermined time passes.

Semiconductor device including current-driven differential driver and method of controlling current-driven differential driver

A clock generating circuit includes: a clock data extracting circuit extracting a clock data signal from a wobble signal detected from an optical disc by passing frequencies around a central frequency, which is changed responsive to the frequency of the wobble signal according to a control signal; and a signal generating circuit generating a recording clock signal, from the clock data signal, having a frequency proportional to a frequency of the wobble signal. An optical disc apparatus incorporates the clock generating circuit.

Clock signal generating device and an optical disc apparatus incorporating the device

A coding circuit for generating an error correction code from digital data to be recorded in a record medium, includes a buffer manager which successively reads the digital data m bytes at a time from a temporal storage memory in a main scan direction and in a sub-scan direction, a PI parity unit which processes the data m bytes at a time, as the m bytes are supplied from the buffer manager, and generates a PI sequence parity based on the data for one row extending in the main scan direction, and a PO parity unit which includes in operation units, each of which processes a corresponding byte of the data, as m bytes of the digital data are supplied from the buffer manager, and generates a PO sequence parity based on the data for one column extending in the sub-scan direction.

An information record and playback apparatus configured to perform record and playback operations of an optical disk which is provided with data recording tracks having a surface wobbled at a predetermined frequency and a plurality of prepits formed with a predetermined phase relation to the position for data recording. The apparatus includes at least a demodulation circuit which operates for a predetermined error flag be indicated at the position of the assumed LPP data bit, when the error pattern is detected to be other than '1' or '0', that may be caused, for example, by noise. Erasure correction with the Reed-Solomon code therefore becomes feasible using the error flag. This achieves error correction of a number of errors even using fewer added data, thereby offering advantages in increasing efficiency in the error correction.

Information record and playback apparatus

An optical disk apparatus for use with a recordable optical disk, which is provided with a clock signal generator configured to generate standard clock signals for data recording such that the location of the data recording restart following an interruption on the optical disk coincides precisely with that of finish of the previous recording. Included in the clock signal generator, a second frequency and phase detector is configured to compare the frequency and phase of a frame synch signal with those of the signal obtained by the 1/588 division of channel clock signals, and control a variable divider to set its dividing ratio 1/50 so as to increase the frequency of channel clock signals, when the interval between frame synch signals is smaller than the period of the 588 channel clocks; while to set the ratio 1/48 to decrease the frequency of channel clock signals, when the interval is larger than the above period.

Optical disk apparatus

A data processing apparatus of an optical disk drive includes a buffer memory which has a page area divided into a plurality of pages, each page having a predetermined size and containing a main data, a subcode and an error code within the page, each page corresponding to one sector of digital data produced by the disk drive with respect to a compact digital disk, an address of each page of the buffer memory being specified by a page number. A buffer management unit accesses data of a particular page of the buffer memory in response to an input address, the input address specifying a starting address of the data of the particular page of the buffer memory. A system control unit having a page register generates the input address by combining a page number stored by the page register with a predetermined offset, and supplies the input address to the buffer management unit when the data of the buffer memory is accessed, the offset being determined in accordance with the data to be accessed, the page number specifying a starting address of the particular page of the buffer memory, the offset specifying a location of the data to be accessed in the particular page relative to the starting address.

Data processing apparatus using paged buffer memory for efficiently processing data of a compact digital disk

An optical pickup apparatus in which a laser beam reflected from an optical memory medium is separated and incident to a light-receiving element having a plurality of divided light-receiving faces and a focusing error signal is formed on the basis of a difference signal provided by a predetermined combination of light-receiving signals outputted from the respective light-receiving faces of the light-receiving element, comprises a bias signal forming device for forming a bias signal in accordance with a reflectance ratio of the optical memory medium based on a sum of the light-receiving signals outputted from the respective light-receiving faces of the light-receiving element; and a device for superimposing the bias signal on the focusing error signal in an accessing stand-by state with respect to the optical memory medium.

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Toyonaka, Japan

Isamu Moriwaki