Fujitsu Corporation

Fujitsu Vlsi Limited

Isamu Kobayashi

Yoshiharu Kato

Yasuhiro Yamamoto

Hajime Sato

Teruo Seki

Hiroyuki Sugamoto

Kenji Nagai

Syuichi Saito

Yasunori Murase

Takahiro Yokoyama

A semiconductor device, a testing method and a refresh control method having a temperature detecting function to detect a predetermined temperature with little dispersion and to optimize the acting state in accordance with the predetermined temperature detected. The semiconductor device includes at least a memory cell, a refresh control circuit for switching the refresh period tREF of the memory cell, and a temperature detecting unit to be biased with a bias voltage VB&plus; coming from a voltage bias unit including a reference unit and a regulator unit.

Semiconductor device having temperature detecting function, testing method, and refresh control method of semiconductor storage device having temperature detecting function

A drive power supply method for a semiconductor device is provided. The semiconductor device has an internal supply voltage generating circuit. First and second internal circuits are connected to the internal supply voltage generating circuit. Drive power is supplied to the first and second internal circuits from the internal supply voltage generating circuit. The second internal circuit operates in standby mode, power-down mode and active mode, so that the internal supply voltage is stably retained in the standby mode or power-down mode, and the consumed current is reduced.

Drive power supplying method for semiconductor memory device and semiconductor memory device

The internal supply voltage generating circuit includes a level trimming circuit for regulating a first reference voltage and generating a predetermined second reference voltage, and an internal reference voltage generating circuit connected to the level trimming circuit, for generating internal reference voltages using the predetermined second reference voltage. The internal supply voltage generating circuit prevents the circuit area from increasing, reduces a variation in a load when regulating a feedback voltage, and generates a plurality of highly accurate internal supply voltages.

Internal supply voltage generating circuit and method of generating internal supply voltage using an internal reference voltage generating circuit and voltage-drop regulator

A semiconductor device which is capable of shutting off the influence of noise introduced into a reference voltage while preventing an increase in die size. The semiconductor device including a reference potential generator, first and second filter, and first and second input circuit. The reference potential generator generates a reference potential in accordance with a first power supply. The first filter is connected to the first power supply and filters the reference potential to generate a first filtered reference potential. The second filter is connected to a second power supply and filters the reference potential to generate a second filtered reference potential. The first input circuit is connected to the first power supply and receives the first filtered reference potential to generate a first predetermined voltage. The second input circuit is connected to the second power supply and receives the second filtered reference potential to generate a second predetermined voltage.

Semiconductor device

A starting circuit for an integrated circuit (IC) device insures that the IC device is properly initialized before an initialization signal is dropped. The starting circuit, which receives power from high and low potential power supplies, includes a first transistor having a threshold voltage within a known range. The first transistor receives a control voltage generated from the high and low potential power supplies and produces a start (initialization) signal, from the time that the high potential power supply voltage begins to rise to when the control voltage rises to the first transistor threshold voltage. A correction circuit connected to the first transistor adjusts the control voltage in accordance with the threshold voltage of the first transistor.

Starting circuit for integrated circuit device

An internal power supply auxiliary circuit supplies a current to a power generator circuit. A pulse signal generator receives an input signal and outputs a first control signal. A driver circuit connected to the pulse signal generator receives the first control signal, an external supply voltage and a source voltage, and generates a drive pulse signal. A current supply driver circuit receives the drive pulse signal and the external supply voltage and outputs the supply current to the power generator circuit. A gate voltage regulator circuit connected to the driver circuit receives a reference voltage and produces the source voltage. The gate voltage regulator causes the source voltage to substantially match the reference voltage so that the current supplied to the power generator circuit does not exceed a predetermined value.

Power supply auxiliary circuit

A power supply circuit for supplying a semiconductor memory device with power to perform refreshing. The power supply circuit is connected to an external power supply. The power supply circuit includes a first power supply circuit, which generates a step down voltage by decreasing a first voltage on the external power supply in a normal operation mode, a second power supply circuit, which supplies the internal circuit with a second voltage on the external power supply in a self-refresh mode, and a detection circuit, which detects entry to the self-refresh mode and a voltage level of the external power supply and generates a detection signal based on the detection. During the self-refresh mode, the first power supply circuit receives the second voltage from the external power supply, and the first and second power supply circuits supply the internal circuit with the second voltage based on the detection signal.

Circuit and method for supplying internal power to semiconductor memory device

A method for controlling an internal supply voltage generating circuit reduces power consumption in an active mode. The internal supply voltage generating circuit includes a first voltage-drop regulator, which supplies a relatively large driving power to an internal circuit, and a second voltage-drop regulator, which supplies a relatively small driving power to the internal circuit. First, the second voltage-drop regulator is activated and the first voltage-drop regulator is inactivated in one of a stand-by mode and a power-down mode. Then, at least the first voltage-drop regulator is activated in an active mode, and the first voltage-drop regulator is inactivated in an active pause of the active mode. The first voltage-drop regulator is activated when the active pause is cancelled.

Internal supply voltage generating cicuit in a semiconductor memory device and method for controlling the same

A two stage charge pump circuit can perform either a two stage boosting operation or a single stage boosting operation. The charge pump circuit includes first, second and third gate transistors connected in series between first and second supply voltages, and a bypass transistor. A first booster stage includes a capacitor connected between the first and second gate transistors and a drive circuit. A second booster stage includes a capacitor connected between second and third gate transistors and the drive circuit. The third gate transistor is connected to an internal bus which provides an output voltage to other circuit elements connected to it. The bypass transistor is connected between the first booster stage and the internal bus.

Charge pump circuit with bypass transistor

A pulse signal shaper supplying a pulse signal having a stable pulse width, including an input circuit that produces a first pulse signal in response to an input signal, a delay circuit that produces a second pulse signal obtained by delaying the first pulse signal by a predetermined time, and a signal mixing circuit that is connected to the input circuit and the delay circuit. The mixing circuit combines the first pulse signal and the second pulse signal to produce a third pulse signal having a pulse width equal to or greater than a delay time provided by the delay circuit, and supplies the third pulse signal as an output signal from the pulse signal shaper. In a preferred embodiment, the input circuit includes an oscillator responsive to the input signal. When the input signal has a higher frequency than a predetermined frequency, the input signal is supplied as the first pulse signal at a frequency equal to te frequency of the input signal. When the input signal has a lower frequency than the predetermined frequency, the first pulse signal is supplied at the predetermined frequency.

Pulse signal shaper in a semiconductor integrated circuit

A data transfer circuit device including a data transfer circuit, a latch control circuit and a data latch circuit. The data transfer circuit outputs data therefrom in response to an externally supplied transfer signal. The latch control circuit generates a data latch signal, based on the transfer signal and a latch control signal. The data latch circuit latches the data supplied from the data transfer circuit, based on the data latch signal, and outputs the latched data as output data. When the data is being switched, the latch control circuit prevents the data latch signal from being supplied to the data latch circuit.

Data transfer circuit device

A output buffer circuit incorporates an output controller and voltage controller between a first and a second voltage potential to buffer the output of data produced by a semiconductor device. The output controller provides switching control signals to transistors in the voltage controller in order to prevent the first potential from being effected by the potential at the output of the output buffer.

Output buffer circuit for semiconductor device

An input protection circuit includes a conductor pattern extending from a first end connected to an input pad to a second end connected to an integrated circuit, first and second, mutually separated ground patterns disposed at both sides of the conductor pattern with a separation therefrom, a first gate pattern provided on a gap between the conductor pattern and the first ground pattern, and a second gate pattern provided on a gap between the conductor pattern and the second ground pattern, wherein the conductor pattern, the first ground pattern and the first gate pattern form a first transistor extending continuously from the first end to the second end of the conductor pattern at a first side of the conductor pattern, and wherein the conductor pattern, the second ground pattern and the second gate pattern form a second transistor extending continuously from the first end to the second end of the conductor pattern at a second side of the conductor pattern.

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Kasugai, Japan

Isamu Kobayashi