Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Mitsubishi Electric Engineering Company, Limited

Isamu Hayashi

Naoya Watanabe

Katsumi Dosaka

Fukashi Morishita

Harufusa Kondoh

Mihoko Akiyama

Teruhiko Amano

Kenji Yoshinaga

Shinya Miyazaki

Masakazu Ishibashi

Akira Yamazaki

Hideyuki Noda

Yoshio Matsuda

Hiromi Notani

Takeshi Fujino

Masaru Haraguchi

Hiroyuki Kawai

Kazutami Arimoto

Hiroki Shimano

Atsuo Mangyo

Masashi Matsumura

The data processing system has: a plurality of hardware resources each having at least one standby mode; a control part for controlling execution of a task achieved by using, of the plurality of hardware resources, predetermined ones, and a working status of each hardware resource; and a power-source part for controlling supply of a power source to each hardware resource. The control part performs the scheduling of a scheduled execution time of the task based on information for determining a timing of executing the task, and calculates a standby time of the hardware resource based on a result of the scheduling. The control part compares the standby time with a break-even time depending on the standby mode, thereby deciding whether or not to cause each hardware resource to transition to the standby mode.

Data processing system with selective engagement of standby mode based on comparison with a break-even time

An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Content addressable memory with reduced power consumption and increased search operation speed

In order to perform easily power cutoff of a device configuring a data processing system and to improve the power reduction effect at standby, the data processing system is configured with a microcontroller, a memory IC including a nonvolatile RAM array, and a power supply unit capable of controlling the power supply to the microcontroller and the memory IC, separately. When a control signal to control read and write of data to the nonvolatile RAM array is at a high level, the memory IC is enabled read and write of data to the nonvolatile RAM array. When the control signal is at a low level, the memory IC is disenabled read and write of data to the nonvolatile RAM array. The microcontroller sets the control signal at a low level, when the memory IC is shifted to a standby state by the power supply unit.

Data processing system, microcontroller and semiconductor device

Content addressable memory

An object is to provide a method for preventing the occurrence of variations in time resolution by providing a calibration process to a TDC at the time of start up and further preventing the increase in circuit scale by reducing the redundancy of delay elements. A calibration of a multiphase oscillator TDC and a vernier TDC is carried out at the time of power-on. In the calibration, a timing input to be input to the vernier TDC is selected from output signals of DCCO based on a reference clock. Also, data is defined as an output signal which is adjacent to the output signal of DCCO mentioned above and proceeds in phase, and the delay therebetween is derived. By repeating it to all of the output signals, the one cycle of the output signal of DCCO is derived.

Clock oscillator circuit and semiconductor device

A retrievable memory is provided with a priority encoder. The priority encoder is constituted by encoder units. Each of the encoder units is constituted by an inverter, N-channel MOS transistors and an AND gate. Upon receipt of a signal of H level from a matching line, the encoder unit outputs a signal of H level to a word line, and also outputs a signal of L level to a matching line active signal line MLA . Then, the encoder units respectively output signals of L level to the word lines. Consequently, even when a plurality of results of a retrieving process are obtained, it is possible to output single data.

Retrievable memory capable of outputting a piece of data with respect to a plurality of results of retrieve

Read data line pairs, write data line pairs, a spare read data line pair, and a spare write data line pair are provided extending in the column direction over a memory cell array. Spare bit repair is performed by replacing a data line pair. Column redundancy control circuit changes the timing for outputting the result of spare determination for a data write mode and for a data read mode. A semiconductor memory device suitable for merging with a logic and capable of reducing the current consumption and achieving a higher operation frequency is provided.

Semiconductor memory device suitable for merging with logic

In an internal clock signal generation circuit, a plurality of internal clock signals of different phases are generated based on an external clock signal. The internal clock signals are synchronized with the external clock signal by a PPL circuit. The plurality of internal clock signals are respectively supplied to a plurality of internal circuit blocks. Since the phases of the generated internal clock signals are different the phases of the internal clock signals arriving at the internal circuit blocks can be matched even if delays of the signals between the internal clock signal generation circuit and the plurality of internal circuit blocks are different. Thus, clock skews between the plurality of internal clock signals can be reduced and the phase of the internal clock signal and the phase of the external clock signal can be synchronized.

Semiconductor integrated circuit device

A data transfer controller (,) decides that both of a host bus (,) and a local bus (,) have been acquired by a bus interface LSI,by the fact that a host bus use permission GNTH from a host bus arbiter (,) and a local bus use permission GNTL from a local bus arbiter (,) are both activated, in which case, the data transfer controller (,) controls a host bus DMA controller (,) and a local bus DMA controller (,) to make selectors SE,and SE,establish a connection between the host bus (,) and the local bus (,) through an inner data path (,) having no buffer. This configuration improves data transfer rate through the host bus (,) and the local bus (,).

Bus control device

An output buffer receives a voltage from a first power supply pin receiving an external power supply voltage for operation. Delay circuits included in an array control circuit, a read control circuit, a write control circuit and an internal clock generation circuit receive a voltage from a second power supply pin receiving the external power supply voltage for operation. Thus, a timing control is accurately performed for reading/writing a data signal without being affected by the change in power supply voltage due to an operation of the output buffer.

Semiconductor memory device having delay circuit for controlling timing

A semiconductor integrated circuit device includes an SDRAM module operating in synchronization with a clock signal, a logic circuit transmitting data with the SDRAM module for effecting necessary processing, a direct memory access circuit taking in and transferring an externally applied signal in synchronization with the clock signal corresponding to an operation clock of the SDRAM module, and a selector selecting either the output signal of the logic circuit and the output signal of the direct memory access circuit in accordance with a test mode instructing signal for application to the SDRAM module. A test of a synchronous memory can be performed by externally making fast and direct access to the synchronous memory without an influence of a skew in a signal.

Clock synchronous memory embedded semiconductor integrated circuit device

The object of the present invention is to obtain a communication device which improves latency and throughput in data transfer processing by reducing the number of accesses to a local bus. A bus interface 1a receives an user data from an AALLSI 4, and, when a host bus cannot be occupied, temporarily stores the user data in a data receiving buffer area 11. The capacity of the data receiving buffer area 11 in the bus interface 1a is set so as not to be full during normal data processing.

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Tokyo, Japan

Isamu Hayashi