Elpida Memory, Inc.

Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Isamu Fujii

Hiroki Fujisawa

Yuko Watanabe

Shinichi Miyatake

Homare Sato

Kouichiro Ninomiya

A semiconductor device includes a plurality of signal lines which are arranged at a predetermined pitch; first and second MOS transistors which are connected to the signal lines, and also serially connected to each other; and a connection device which functions as a connection node between the serially-connected first and second MOS transistors, and connects a source area of one of the first and second MOS transistors to a drain area of the other of the first and second MOS transistors via contact holes, which are formed through an insulating layer, and a conduction layer connected to the contact holes.

Semiconductor device having MOS transistors which are serially connected via contacts and conduction layer

Disclosed is a semiconductor memory device comprising a memory cell array block, and a circuit region arranged with the memory cell array block along a first direction. The circuit region comprises a first region and a second region arranged with the first region along the first direction. The first region is provided with a first circuit and a second circuit which are aligned in a second direction perpendicular to the first direction. The second region is provided with a plurality of third circuits which are aligned in the second direction.

Semiconductor memory device

A semiconductor memory device is capable of performing a faster operation by reducing a load applied to a subword selection line or driving a subword driver provided for each memory mat. In a drive method of subword drivers that are actuated in response to subword selection signals supplied through subword selection lines, the subword selection lines are branched according to the number of memory mats. Each subword selection signal has a polarity to a branching position and an inverted polarity from each branching position to each subword driver. The inverted subword selection signal together with a main word signal are calculated to operation in each subword driver and output as a subword drive signal. The plurality of subword drivers share an inverter circuit for inverting the main word signals so as to permit a simplified circuit configuration.

Semiconductor memory device including subword drivers

Growing community of inventors

Kodaira, Japan

Isamu Fujii