Hitachi, Ltd.

Elpida Memory, Inc.

Other

Hitachi Vlsi Engineering Corp.

Texas Instruments Corporation

Hitachi Ulsi Systems Co., Ltd.

Ovonyx Inc.

Hitachi Ulsi Engineering Corp.

Hiatchi, Ltd.

Isamu Asano

Hideo Aoki

Tsuyoshi Tamaru

Yoshitaka Nakamura

Masakazu Sagawa

Mitsuaki Horiuchi

Jun Sugiura

Hidetsugu Ogishi

Satoru Yamada

Yoshitaka Tadaki

Osamu Tsuchiya

Keizo Kawakita

Hidekazu Goto

Makoto Yoshida

Yoshinao Kawasaki

Nobuo Owada

Toru Kaga

Fumio Ootsuka

Kazuyoshi Torii

Hiromichi Enami

Osamu Kasahara

Makoto Ogasawara

Keisuke Funatsu

Masatoshi Tsuneoka

Takayoshi Kogano

Seiichirou Shirai

Atsushi Wakahara

Hiroyuki Akimori

Sinichi Suzuki

Nobuhiro Otsuka

Yoshihiro Ikeda

Tomotsugu Shimmyo

Tunehiko Tubone

Ken Tsugane

Toshihiro Sekiguchi

Naoki Fukuda

Masayoshi Hirasawa

Robert Yung-Hsi Tsu

Masayoshi Saito

Tsuyoshi Kawagoe

Tomio Iwasaki

Hiroshi Sakuma

Kazuhiko Kajigaya

Naoki Yamamoto

Yoshikazu Tanabe

Kiyoshi Nakai

Nobuyoshi Natsuaki

Atsushi Hiraiwa

Shinji Shimizu

Jun Murata

Hiroko Kaneko

Masami Ozawa

Hideo Miura

Hiroyuki Ohta

Shinpei Iijima

Yukio Fuji

Takahiro Kumauchi

Katsuhiko Tanaka

Tyler A Lowrey

William R McKee

Natsuki Sato

Takuya Fukuda

Yuzuru Ohji

Keizou Kawakita

Tomonori Sekiguchi

Norio Hasegawa

Wolodymyr Czubatyj

Masayuki Suzuki

Yukihiro Kumagai

Riichiro Takemura

Hideyuki Matsuoka

Junji Tominaga

Nobuyoshi Kobayashi

Ryo Nagai

Hiroshi Moriya

Takashi Yunogami

Jeffrey A McKee

Paul Fons

Keiji Kuroki

Alexander Kolobov

Akiyoshi Seko

Tadashi Umezawa

Robert Simpson

Kazuo Aizawa

Stephen J Hudgens

Guy Charles Wicker

Chih-Chen Cho

Tsugio Takahashi

Tatsuyuki Saito

Kenichi Koyanagi

Mitsuhiro Horikawa

Tomoyasu Kakegawa

Yuta Watanabe

Jing Shing Shu

Naoya Higano

Yoshikazu Ohira

Masato Kunitomo

Shimpei Iijima

Jeffrey P Fournier

Disclosed herein is a device that includes: an interlayer insulation film having a through hole; and a phase change storage element provided in the through hole. The phase change storage element includes: an outer electrode being a conductive film of cylindrical shape and being formed along an inner wall of the through hole; a buffer insulation film being an insulation film of cylindrical shape and being formed along an inner wall of the outer electrode, an upper end of the buffer insulation film being recessed in part to form a recess; a phase change film filling an interior of the recess; and an inner electrode being a conductive film formed along an inner wall of the buffer insulation film including a surface of the phase change film.

Semiconductor device including phase change material and method of manufacturing same

A semiconductor device may include, but is not limited to: a first insulating film; a second insulating film over the first insulating film; a first memory structure between the first and second insulating films; and a third insulating film between the first and second insulating films. The first memory structure may include, but is not limited to: a heater electrode; and a phase-change memory element between the heater electrode and the second insulating film. The phase-change memory element contacts the heater electrode. The third insulating film covers at least a side surface of the phase-change memory element. Empty space is positioned adjacent to at least one of the heater electrode and the third insulating film.

Semiconductor device including a phase-change memory element

To include a superlattice laminate having laminated thereon a first crystal layer of which crystal lattice is a cubic crystal and in which positions of constituent atoms are reversibly replaced by application of energy, and a second crystal layer having a composition different from that of the first crystal layer, and an orientation layer that is an underlaying layer of the superlattice laminate and causes a laminated surface of the first crystal layer to be (111)-orientated. According to the present invention, the laminated surface of the first crystal layer can be (111)-orientated by using the orientation layer as an underlaying layer. In the first crystal layer of which laminated surface is (111)-orientated, a crystal structure reversibly changes when a relatively low energy is applied. Therefore, characteristics of a superlattice device having this crystal layer can be enhanced.

Superlattice device, manufacturing method thereof, solid-state memory including superlattice device, data processing system, and data processing device

A solid-state memory device includes: a superlattice laminate having plural crystal layers laminated therein, the crystal layers including first and second crystal layers having mutually opposite compositions; a lower electrode provided on a first surface in a laminating direction of the superlattice laminate; and an upper electrode provided on a second surface of the superlattice laminate in the laminating direction. The first crystal layer included in the superlattice laminate is made of a phase change compound. According to the present invention, the superlattice laminate laminated in opposite directions of the upper and lower electrodes is sandwiched between these electrodes. Therefore, when an electric energy is applied to the superlattice laminate via these electrodes, a uniform electric energy can be applied to a laminated surface of the superlattice laminate. Accordingly, fluctuation of a resistance is small even when information is repeatedly rewritten, and data can be read stably as a result.

Solid-state memory device, data processing system, and data processing device

A nonvolatile memory device () is provided with a semiconductor substrate, a plurality of active regions () formed on the semiconductor substrate and extending in a band, a plurality of select active elements () formed in the active regions () and having a first impurity diffusion region and a second impurity diffusion region, a plurality of first electrodes () electrically connected to the first impurity diffusion region, a variable resistance layer () electrically connected to the first electrodes (), and a plurality of second electrodes electrically connected to the variable resistance layer (). Among the plurality of first electrodes () and the plurality of second electrodes, an array direction of at least one pair of the first electrodes () and the second electrodes that are electrically connected to the same variable resistance layer (), and a direction of extension of the activation regions () are not parallel.

Nonvolatile memory device

An area where a lower electrode is in contact with a variable resistance material needs to be reduced to lower the power consumption of a variable resistance memory device. The present invention is to provide a method of producing a variable resistance memory element whereby the lower electrode can be formed smaller. Combining an anisotropic etching process with an isotropic etching process enables the lower electrode to be formed smaller.

Method of producing phase change memory device

A radial memory device includes a phase-change material, a first electrode in electrical communication with the phase-change material, the first electrode having a first area of electrical communication with the phase-change material. A second electrode in electrical communication with the phase-change material, the second electrode having a second area of electrical communication with the phase-change material, and the second area being laterally spacedly disposed from the first area. Additionally, the radial memory device includes a dielectric layer disposed between the first electrode and the second electrode, the dielectric layer having an opening therethrough, the phase-change material being disposed in the opening, wherein the phase-change material is disposed at least partially above the second electrode. Further, a method of making a memory device is disclosed.

Memory device and method of making same

A non-volatile memory element comprises a bottom electrode; a top electrode; and a recording layercontaining phase change material and a block layerthat can block phase change of the recording layer, provided between the bottom electrodeand the top electrode. The block layeris constituted of material having an electrical resistance that is higher than that of material constituting the recording layer. The block layersuppresses the radiation of heat towards the top electrodeand greatly limits the phase change region when a write current is applied. The result is a high heating efficiency. The top electrodeitself can be used to constitute a bit line, or a separate bit line can be provided.

Electrically rewritable non-volatile memory element and method of manufacturing the same

A phase change memory device, comprising a phase change memory device; a semiconductor substrate; a MOS transistor disposed at each intersection of a plurality of word lines and a plurality of bit lines arranged in a matrix form; a plurality of phase change memory elements for storing data of a plurality of bits, each formed on an upper area opposite to a diffusion layer of the MOS transistor in a phase change layer made of phase change material; a lower electrode structure for electrically connecting each of the plurality of phase change memory elements to the diffusion layer of the MOS transistor.

Phase change memory device

A non-volatile memory element comprising a bottom electrode, a top electrodeprovided on the bottom electrode, and a recording layercontaining phase change material connected between the bottom electrodeand the top electrode. In accordance with this invention, the top electrodeis in contact with a growth initiation surface 18of the recording layer. This structure can be obtained by forming the top electrodebefore the recording layer, resulting in a three-dimensional structure. This decreases heat dissipation to the bit line without increasing the thickness of the recording layer

A non-volatile memory element includes a first interlayer insulation layerhaving a first through-hole, a second interlayer insulation layerhaving a second through-holeformed on the first interlayer insulation layer, a bottom electrodeprovided in the first through-hole, recording layercontaining phase change material provided in the second through-hole, a top electrodeprovided on the second interlayer insulation layer, and a thin-film insulation layerformed between the bottom electrodeand the recording layer. In accordance with this invention, the diameter Dof a bottom electrodeburied in a first through-holeis smaller than the diameter Dof a second through-hole, thereby decreasing the thermal capacity of the bottom electrode. Therefore, when a poreis formed by dielectric breakdown in a thin-film insulation layerand the vicinity is used as a heating region, the amount of heat escaping to the bottom electrodeis decreased, resulting in higher heating efficiency.

A non-volatile memory element includes a lower electrode, an upper electrode, a recording layer arranged between the lower electrode and the upper electrode and containing a phase change material, and a bit line directly arranged on the upper electrode. The bit line is formed to be offset to the recording layer. With this arrangement, a contact area between the recording layer and the upper electrode and a contact area between the upper electrode and the bit line can be reduced without providing an interlayer insulation film between the upper electrode and the bit line. Thus, heat radiation to the bit line can be suppressed while the upper electrode and the bit line are connected without using a through-hole.

A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM bit line. The memory device further has a capacitive element disposed on the upper layer of the DRAM bit line, and a phase-change element disposed on the upper layer of the PCRAM bit line. The lower electrode of the capacitive element and the lower electrode of the phase-change memory element are formed on the shared conductive layer.

Memory device and manufacturing method thereof

In a semiconductor memory comprising a matrix of memory cells each composed of one transistor and one chalcogenide layer as a memory element, no chalcogenide layer is disposed at a joint between an upper electrode wire connected to the chalcogenide layer and another wiring layer.

Semiconductor memory

A non-volatile memory element includes a bottom electrode, a bit lineprovided on the bottom electrode, and a recording layercontaining phase change material connected between the bottom electrodeand the bit line. In accordance with this invention, the bit lineis in contact with a growth initiation surfaceof the recording layer. This structure can be obtained by forming the bit linebefore the recording layer, resulting in a three-dimensional structure. This decreases the area of contact between the recording layerand the bit line, decreasing heat dissipation to the bit linewithout increasing the thickness of the recording layer. With this three-dimensional structure, moreover, there is no top electrode between the bit lineand the recording layer, keeping down the complexity of the fabrication process.

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Iruma, Japan

Isamu Asano