Marvell Asia Pte., Ltd.

Cavium, Inc.

Vmware, Inc.

Isam Wadih Akkawi

David Asher

Richard Eugene Kessler

Shubhendu Sekhar Mukherjee

Pratap Subrahmanyam

Andreas Georg Nowatzyk

David K Carlson

Rajesh Venkatasubramanian

Wilson Parkhurst Snyder, Ii

Bradley D Dobbie

Venkata Subhash Reddy Peddamallu

David Albert Carlson

Michael S Bertone

Irina Calciu

Bryan Chin

Jason Daniel Zebchuk

Thomas Frederick Hummel

Daniel Edward Dever

Craig Barner

Shahid Ikram

James Ellis

Adarsh Seethanadi Nayak

Nishchay Dua

Rabin Sugumar

John M Perveiler

Pranith Kumar Denthumdas

Darren Braun

Srilatha Manne

Xiaodong Wang

Yijiang Yuan

The systems and methods to support flexible reconfiguration of a network chip by an external entity, such as a baseboard management controller (BMC), while maintaining a secured environment for the chip so that it can be booted securely. Specifically, the network chip is configured to designate one or more of its networking ports to the BMC and allow the BMC to configure the designated networking ports without violating the secure areas of the network chip. To this end, the network chip is configured to allow the BMC to access a plurality of registers of the network chip via an Network Controller Sideband Interface (NC-SI) block of the network chip by issuing a plurality NC-SI compliant commands. By configuring the designated networking ports, the BMC is configured to establish a data path to a management software of a platform that includes the network chip though the designated networking ports.

Systems and methods for allowing flexible chip configuration by external entity

Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.

Low latency inter-chip communication mechanism in a multi-chip processing system

A method of prefetching memory pages from remote memory includes detecting that a cache-line access made by a processor executing an application program is an access to a cache line containing page table data of the application program, identifying data pages that are referenced by the page table data, initiating a fetch of a data page, which is one of the identified data pages, and starting a timer. If the fetch completes prior to expiration of the timer, the data page is stored in a local memory. On the other hand, if the fetch does not complete prior to expiration of timer, a presence bit of the data page in the page table data is set to indicate that the data page is not present.

Smart prefetching for remote memory

The state of cache lines transferred into an out of caches of processing hardware is tracked by monitoring hardware. The method of tracking includes monitoring the processing hardware for cache coherence events on a coherence interconnect between the processing hardware and monitoring hardware, determining that the state of a cache line has changed, and updating a hierarchical data structure to indicate the change in the state of said cache line. The hierarchical data structure includes a first level data structure including first bits, and a second level data structure including second bits, each of the first bits associated with a group of second bits. The step of updating includes setting one of the first bits and one of the second bits in the group corresponding to the first bit that is being set, according to an address of said cache line.

Method and system for tracking state of cache lines

A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.

Methods and systems for distributing memory requests

In one set of embodiments, a hardware module of a computer system can receive a stream of addresses corresponding to memory units being accessed by a central processing unit (CPU) of the computer system. The hardware module can further generate a frequency estimate for each address in the stream of addresses, the frequency estimate being indicative of a number of times a memory unit identified by the address has been accessed by the CPU, and can determine, based on the generated frequency estimates, a set of n most frequently accessed memory units.

Techinques for tracking frequently accessed memory

In a computer system, a processor and an I/O device controller communicate with each other via a coherence interconnect and according to a cache coherence protocol. Registers of the I/O device controllers are mapped to the cache coherent memory space to allow the processor to treat the registers as cacheable memory. As a result, latency of processor commands executed by the I/O device controller is decreased, and size of data stored in the I/O device controller that can be accessed by the processor is increased from the size of a single register to the size of an entire cache line.

Low latency host processor to coherent device interaction

In a multi-node system, each node includes tiles. Each tile includes a cache controller, a local cache, and a snoop filter cache (SFC). The cache controller responsive to a memory access request by the tile checks the local cache to determine whether the data associated with the request has been cached by the local cache of the tile. The cached data from the local cache is returned responsive to a cache-hit. The SFC is checked to determine whether any other tile of a remote node has cached the data associated with the memory access request. If it is determined that the data has been cached by another tile of a remote node and if there is a cache-miss by the local cache, then the memory access request is transmitted to the global coherency unit (GCU) and the snoop filter to fetch the cached data. Otherwise an interconnected memory is accessed.

System and methods for reducing global coherence unit snoop filter lookup via local memories

Techniques for implementing hardware-assisted memory disaggregation with recovery from network failures/problems are provided. In one set of embodiments, a hardware controller of a computer system can maintain a copy of a 'remote memory' of the computer system (i.e., a section of the physical memory address space of the computer system that maps to a portion of the physical system memory of a remote computer system) in a local backup memory. The backup memory may be implemented using a non-volatile memory that is slower, but also less expensive, than conventional dynamic random-access memory (DRAM). Then, if the hardware controller is unable to retrieve data in the remote memory from the remote computer system within a specified time window due to, e.g., a network failure or other problem, the hardware controller can retrieve the data from the backup memory, thereby avoiding a hardware error condition (and potential application/system crash).

Hardware-assisted memory disaggregation with recovery from network failures using non-volatile memory

Memory pages of a local application program are prefetched from a memory of a remote host. A method of prefetching the memory pages from the remote memory includes detecting that a cache-line access made by a processor executing the local application program is an access to a cache line containing page table data of the local application program, identifying data pages that are referenced by the page table data, and fetching the identified data pages from the remote memory and storing the fetched data pages in a local memory.

Growing community of inventors

Santa Clara, CA, United States of America

Isam Wadih Akkawi