Huawei Technologies Co., Limited

3 Leaf Systems, Inc.

3 Leaf Networks

Isam Akkawi

Bryan Chin

Najeeb Imran Ansari

Krishnan Subramani

Chetana Nagendra Keltcher

Shahe Hagop Krakirian

Robert Quinn

Scott A Lurndal

Ushasri Sunkara

Michael Woodacre

Janakiramanan Vaidyanathan

Methods, apparatuses and systems directed to virtualized access to input/output (I/O) subsystems. In one implementation, the present invention allows multiple stand-alone application servers or virtual servers to share one or more I/O subsystems, such as host-bus adapters and network interface cards. In one implementation, I/O access is managed by one or more virtual I/O servers. A virtual I/O server includes a multiplexer, and associated modules, that connect application servers over an I/O switch fabric with one or more HBA and/or NIC drivers. Implementations of the present invention can be configured to consolidate I/O access, allowing multiple servers to share one or more HBAs and NICs; dynamic control over network and storage I/O bandwidth; and provisioning of network and storage I/O access across multiple application servers.

Virtual input/output server

An example embodiment of the present invention provides processes relating to a connection/communication protocol and a memory-addressing scheme for a distributed shared memory system. In the example embodiment, a logical node identifier comprises bits in the physical memory addresses used by the distributed shared memory system. Processes in the embodiment include logical node identifiers in packets which conform to the protocol and which are stored in a connection control block in local memory. By matching the logical node identifiers in a packet against the logical node identifiers in the connection control block, the processes ensure reliable delivery of packet data. Further, in the example embodiment, the logical node identifiers are used to create a virtual server consisting of multiple nodes in the distributed shared memory system.

Node identification for distributed shared memory system

An example embodiment of the present invention provides processes relating to a cache coherence protocol for distributed shared memory. In one process, a DSM-management chip receives a request to modify a block of memory stored on a node that includes the chip and one or more CPUs, which request is marked for fast invalidation and comes from one of the CPUs. The DSM-management chip sends probes, also marked for fast invalidation, to DSM-management chips on other nodes where the block of memory is cached and responds to the original probe, allowing the requested modification to proceed without waiting for responses from the probes. Then the DSM-management chip delays for a pre-determined time period before incrementing the value of a serial counter which operates in connection with another serial counter to prevent data from leaving the node's CPUs over the network until responses to the probes have been received.

Fast invalidation for cache coherency in distributed shared memory system

Growing community of inventors

Aptos, CA, United States of America

Isam Akkawi