Soitec

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Applied Materials, Inc.

Isabelle Bertrand

Oleg Kononchuk

Christophe Maleville

Walter Schwarzenbach

Luciana Capello

Marcel Broekaart

Frédéric Allibert

Patrick Reynaud

Christelle Veytizou

Emmanuel Augendre

Daniel Delprat

Frédéric Gaillard

Emmanuel Rolland

Lamia Nouri

Alexis Drouin

Isabelle Huyet

Damien Massy

Young-Pil Kim

Eric Butaud

Sothachett Van

Alexandre Chibko

Morgane Logiou

Norbert Colombet

Thomas Lorne

Sylvain Peru

Oleg Kononchuck

Aymen Ghorbel

Youngpil Kim

Chee Hoe Wong

YoungPil Kim

A method for manufacturing a structure comprising a thin layer transferred onto a support provided with a charge trapping layer, the method comprising the following steps: —preparing the support comprising forming the trapping layer on a base substrate, the trapping layer having a hydrogen concentration of less than 10{circumflex over ( )}18 at/cm{circumflex over ( )}; —joining the support to a donor substrate by way of a dielectric layer having a hydrogen concentration of less than 10{circumflex over ( )}20 at/cm{circumflex over ( )}3 or comprising a barrier preventing the diffusion of hydrogen toward the trapping layer or having low hydrogen diffusivity; —removing part of the donor substrate to form the thin layer; the manufacturing method exposing the structure to a temperature below a maximum temperature of 1000° C. The present disclosure also relates to a structure obtained at the end of this method.

Method for manufacturing a structure comprising a thin layer transferred onto a support provided with a charge trapping layer

A handle substrate for a composite structure comprises a base substrate including an epitaxial layer of silicon on a monocrystalline silicon wafer obtained by Czochralski pulling, a passivation layer on and in contact with the epitaxial layer of silicon, and a charge-trapping layer on and in contact with the passivation layer. The monocrystalline silicon wafer of the base substrate exhibits a resistivity of between 10 and 500 ohm·cm, while the epitaxial layer of silicon exhibits a resistivity of greater than 2000 ohm·cm and a thickness ranging from 2 to 100 microns. The passivation layer is amorphous or polycrystalline. A method is described for forming such a substrate.

Method for forming a handling substrate for a composite structure intended for RF applications and handling substrate

A semiconductor structure for radio frequency applications includes a support substrate made of silicon and comprising a mesoporous layer, a dielectric layer arranged on the mesoporous layer and a superficial layer arranged on the dielectric layer. The mesoporous layer comprises hollow pores, the internal walls of which are mainly lined with oxide. The mesoporous layer has a thickness between 3 and 40 microns and a resistivity greater than 20 kohm·cm over its entire thickness. The support substrate has a resistivity between 0.5 and 4 ohm·cm. The invention also relates to a method for producing such a semiconductor structure.

Semiconductor structure comprising a buried porous layer for RF applications

A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm&#xb7;cm and a thickness greater than 5 microns positioned on the first insulating layer.

Support for a semiconductor structure

A method of fabrication of a semiconductor element includes a step of rapid heat treatment in which a substrate comprising a base having a resistivity greater than 1000 Ohm&#xb7;cm is exposed to a peak temperature sufficient to deteriorate the resistivity of the base. The step of rapid heat treatment is followed by a curing heat treatment in which the substrate is exposed to a curing temperature between 800&#xb0; C. and 1250&#xb0; C. and then cooled at a cooldown rate less than 5&#xb0; C./second when the curing temperature is between 1250&#xb0; C. and 1150&#xb0; C., less than 20&#xb0; C./second when the curing temperature is between 1150&#xb0; C. and 1100&#xb0; C., and less than 50&#xb0; C./second when the curing temperature is between 1100&#xb0; C. and 800&#xb0; C.

Method of fabrication of a semiconductor element comprising a highly resistive substrate

A process for the manufacture of a semiconductor element includes a stage of rapid heat treatment of a substrate comprising a charge-trapping layer, which is capable of damaging an RF characteristic of the substrate. The rapid heat treatment stage is followed by a healing heat treatment of the substrate between 700&#xb0; C. and 1,100&#xb0; C., for a period of time of at least 15 seconds.

Process for the manufacture of a semiconductor element comprising a layer for trapping charges

A method for fabricating a structure comprising, in succession, a support substrate, a dielectric layer, an active layer, a separator layer of polycrystalline silicon, comprising the steps of: a) providing a donor substrate, b) forming an embrittlement area in the donor substrate, c) providing the support structure, d) forming the separator layer on the support substrate, e) forming the dielectric layer, f) assembling the donor substrate and the support substrate, g) fracturing the donor substrate along the embrittlement area, h) subjecting the structure to a strengthening annealing of at least 10 minutes, the fabrication method being noteworthy in that step d) is executed in such a way that the polycrystalline silicon of the separator layer exhibits an entirely random grain orientation, and in that the strengthening annealing is executed at a temperature strictly greater than 950&#xb0; C. and less than 1200&#xb0; C.

Method for fabricating a structure

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Bernin, France

Isabelle Bertrand