Dell Products Inc.

Isaac Qin Wang

Jordan Chin

Timothy Michael Lambert

Johan Rahardjo

James Lewis Petivan

Qinghong He

Lee B Zaretsky

Milton Olavo Taveira

James L Petivan

Elie Antoun Jreij

Stuart Allen Berke

Rama Rao Bisa

Corey Dean Hartman

Akkiah Choudary Maddukuri

Pavan Kumar Gavvala

Duk Moon Kim

Yeshaswy Rajupalepu

Jing Zhang

Bhyrav M Mutnury

Adolfo Sandor Montero

Sandor Tibor Farkas

Shawn Joel Dube

Robert Boyd Curtis

Anh Dinh Luong

Hang Li

Earl Boone

Ray Vivian Kacelenga

Vinh B Lu

Jeremiah James Bartlett

Wallace Huson Ables

Yunfan Han

Milton Olavo Decarvalho Taveira

Andy Liu

Anthony W Howard

Joshua David Anderson

Yayun Liu

Kevin Matthew Cross

Ronald Paul Rudiak

Justin Whittenberg

Yun Guo

Tim M Spencer

An information handling system includes processing nodes, a compute express link (CXL) switch, and CXL devices. A workload orchestrator receives a workload to be instantiated on a particular one of the processing nodes, determines a set of resources associated with the workload, selects a particular one of the CXL devices to be used based upon the set or resources, and launches the workload on the processing node.

Memory disaggregation in a multi-node environment

Methods and systems for managing operation of data processing systems are disclosed. To manage the operation of the data processing systems, access to information regarding the operation of hardware components of the data processing systems may be provided. The access may be provided by configuring the internal communication topology of the data processing systems. The topologies may be configured to limit access to unvalidated entities, and provide access to validated entities.

System and method for managing access to information regarding operation of hardware components of data processing systems

In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may: provide a first chip select signal to a chip of an information handling system (IHS), which stores at least a portion of IHS firmware, while at least one processor of the IHS is executing processor instructions; determine that a second chip select signal is provided to the chip; provide, to an embedded controller of the IHS, a signal that indicates that the second chip select signal has been provided to the chip; receive a signal to boot the IHS; determine if the embedded controller has received the signal that indicates that the second chip select signal has been provided to the chip; if so, prevent the IHS from booting; and if not, permit the IHS to boot utilizing the at least the portion of the IHS firmware stored by the chip.

System and method of detecting tampering of an information handling system

An interface apparatus for installing an add-in module to an information handling system includes the add-in module and an add-in module socket. The add-in module includes a card-edge connector on a first edge of the add-in module, and an electrical contact finger on a second edge of the add-in module. The add-in module socket is affixed to the information handling system and receives the add-in module. The add-in module socket includes a card-edge connector interface for receiving the card edge connector, and a slot channel for receiving the second edge of the add-in module. The slot channel includes an electrical contact pad configured such that, when the add-in module is installed into the add-in module socket, a current is provided between the add-in module socket and the add-in module through the electrical contact pad and the electrical contact finger.

Memory module connection interface for power delivery

A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.

Power reduction in a clock buffer of a memory module based upon memory module topology

Controlling memory module clock buffer power in a system with a single memory clock per memory module

An interface apparatus for installing memory modules to an information handling system includes a riser card and an adapter. The riser card includes a first card-edge connector on a first edge of the riser card, and a second card-edge connector on a second edge of the riser card. The first card-edge connector is associated with a first interface and the second card-edge connector is associated with a second interface. The adapter includes a first socket on a first side of the adapter, and a second socket on a second side of the adapter opposite to the first side. The first socket and the second socket are associated with the second interface. The first socket is configured to receive the second card-edge connector of the riser card. The second socket is configured to receive a memory module.

CXL memory expansion riser card

An information handling system detects a transition of a signal from a magnetic sensor, wherein the transition of the signal indicates a change of a lid of the information handling system from a first state to a second state. The system may determine an angle of the lid based on information from an inertial sensor, and confirm whether the lid is at the second state based on the determined angle of the lid. In response to a confirmation that the lid is at the second state, the system may perform a power sequence.

Disregarding spurious power-on and power-off triggers

A memory module includes first and second data storage locations. The memory module operates with a full set of functions. When the first data storage location stores an expansion license, the memory module is configurable to operate with a subset of the full set of functions disabled. The second data storage location stores an expansion capability certificate, that is signed by an information handling system and includes a first subset of the full set of functions that are disabled by the expansion capability certificate. The memory module determines that the memory module is installed into the information handling system based on the expansion capability certificate, and disables the first subset of the full set of functions in response to determining that the memory module is installed into the information handling system.

Authentication of memory expansion capabilities

Controlling memory module clock buffer power in a system with dual memory clocks per memory module

An information handling system includes an enclosure configured to include a duct to channel air flow in the enclosure over a first component of the information handling system. A duct sensor determines if the duct is included in the enclosure. The system receives an indication from the duct sensor that the duct is not included in the information handling system, determines that the first component is in a hot spot in the enclosure based upon the indication, and redirects a workload instantiated on the first component to a second component of the information handling system.

Cooling detection and profile for system optimization

An information handling system includes a printed circuit board (PCB) and an integrated circuit device. The integrated circuit device includes a substrate and a die that is bonded via a first surface of the die to a first surface of the substrate. The substrate includes a ball grid array (BGA) on the first surface of the substrate. The integrated circuit device is bonded to a first surface of the PCB via the BGA. The die is collocated with the cutout area.

Ball grid array package design

An information handling system includes a plug-in connector interface and an accelerator module installed into the plug-in connector interface. The plug-in connector interface is located at a location on a printed circuit board of the information handling system. The information handling system instantiates a workload on a processor, and allocates a processing resource of the accelerator module to the workload based upon the plug-in connector interface being located at the location.

Location-based workload optimization

An information handling system includes a processor and a memory module. The memory module operates with a base set of functions and is configurable to operate with an expanded set of functions. The memory module includes a data storage location to store expansion capability certificates that specify subsets of the expanded set of functions to enable. The processor creates an expansion capability certificate that includes a first unique identifier of the information handling system, a second unique identifier of the memory module, and a subset of the expanded set of functions, and provides the expansion capability certificate to the memory module. The memory module receives the first expansion capability certificate, stores the expansion capability certificate to the data storage location, and enables the subset of the expanded set of functions in response to storing the expansion capability certificate.

Information handling system configured for authentication of memory expansion capabilities

Method for power reduction in memory modules

Growing community of inventors

Austin, TX, United States of America

Isaac Qin Wang