International Business Machines Corporation

Globalfoundries Inc.

Other

Adeia Semiconductor Bonding Technologies Inc.

Elpis Technologies Inc.

Isaac Lauer

Jeffrey W Sleight

Josephine B Chang

Michael A Guillorn

Chung-Hsun Lin

Leland Chang

Xin Miao

Gen Pei Lauer

Bruce Bennett Doris

Amlan Majumdar

Szu-Lin Cheng

Jeng-Bang Yau

Jack Oon Chu

Renee Tong Mo

Sarunya Bangsaruntip

Karthik Balakrishnan

Tenko Yamashita

Ghavam G Shahidi

Martin Michael Frank

Ramachandran Muralidhar

Neereja Sundaresan

Alexander Reznicek

Guy M Cohen

Takashi Ando

Nicolas J Loubet

Ying Di Zhang

Kuen-Ting Shiu

Robert H Dennard

David James Frank

Nicholas C Fuller

Shreesh Narasimha

Steven John Koester

Paul S Chang

Jiaxing Liu

Steve Koester

Kangguo Cheng

Ali Khakifirooz

Effendi Leobandung

Kevin K Chan

Paul Michael Solomon

Wilfried Haensch

Min Yang

Dae-Gyu Park

Xinhui Wang

William Francis Landers

David C Mckay

Matthias Steffen

Young-Hee Kim

Oliver Dial

Abhinav Kandala

Szu Lin Cheng

Emily Pritchett

Stephen W Bedell

Eric Andrew Joseph

Nicholas C M Fuller

Katherina E Babich

Sebastian Ulrich Engelmann

Michael Joseph Rooks

Easwar Magesan

James Vichiconti

Srikanth Srinivasan

Joseph S Newbury

Ryan M Martin

Jeffrey N Sleight

Techniques regarding an embedded microstrip transmission line implemented in one more superconducting microwave electronic devices are provided. For example, one or more embodiments described herein can comprise an apparatus, which can include a superconducting material layer positioned on a raised portion of a dielectric substrate. The raised portion can extend from a surface of the dielectric substrate. The apparatus can also comprise a dielectric film that covers at least a portion of the superconducting material layer and the raised portion of the dielectric substrate.

Embedded microstrip transmission line

A field effect transistor (FET) includes a substrate; a channel material located on the substrate, the channel material comprising one of graphene or a nanostructure; a gate located on a first portion of the channel material; and a contact aligned to the gate, the contact comprising one of a metal silicide, a metal carbide, and a metal, the contact being located over a source region and a drain region of the FET, the source region and the drain region comprising a second portion of the channel material.

Graphene/nanostructure FET with self-aligned contact and gate

Techniques for using stark tone pulses to mitigate cross-resonance collision in qubits are presented. A tone management component can control application of pulses to qubits by a tone generator component to mitigate undesirable frequency collisions between qubits. The tone generator component (TGC) can apply an off-resonant tone pulse to a qubit during a gate to induce a stark shift. TGC can apply a cross-resonance tone pulse to a control qubit at a frequency associated with the qubit, wherein the frequency can be stark shifted based on the off-resonant tone pulse. The qubit can be a target qubit, the control qubit itself, or a spectator qubit that can be coupled to the target qubit or the control qubit. The gate can be a cross-resonance gate, a two-qubit gate, or a measurement gate that can utilize an echo sequence, a target rotary, or active cancellation.

Pulsed stark tones for collision mitigation

Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a superconducting circuit provided on an encapsulated vacuum cavity are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise a superconducting circuit provided on the encapsulated vacuum cavity.

Superconducting circuit provided on an encapsulated vacuum cavity

Systems and techniques that facilitate mapping a heavy-hex qubit connection topology to a rectilinear physical qubit layout are provided. In various embodiments, a device can comprise a qubit lattice on a substrate. In various aspects, the qubit lattice can comprise one or more first qubit tiles. In various cases, the one or more first qubit tiles can have a first shape. In various instances, the qubit lattice can further comprise one or more second qubit tiles. In various cases, the one or more second qubit tiles can have a second shape. In various aspects, the one or more first qubit tiles can be tessellated with the one or more second qubit tiles.

Heavy-hex connection topology to rectilinear physical layout

Systems, computer-implemented methods, and/or computer program products that can facilitate target qubit decoupling in an echoed cross-resonance gate are provided. According to an embodiment, a computer-implemented method can comprise receiving, by a system operatively coupled to a processor, both a cross-resonance pulse and a decoupling pulse at a target qubit. The cross-resonance pulse propagates to the target qubit via a control qubit. The computer-implemented method can further comprise receiving, by the system, a state inversion pulse at the control qubit. The computer-implemented method can further comprise receiving, by the system, both a phase-inverted cross-resonance pulse and a phase-inverted decoupling pulse at the target qubit. The phase-inverted cross-resonance pulse propagates to the target qubit via the control qubit.

Target qubit decoupling in an echoed cross-resonance gate

Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a vacuum encapsulated Josephson junction are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise one or more superconducting components of a superconducting circuit provided inside the encapsulated vacuum cavity.

Vacuum encapsulated Josephson junction

Systems, devices, computer-implemented methods, and/or computer program products that facilitate dynamic control of ZZ interactions for quantum computing devices. In one example, a quantum device can comprise a biasing component that is operatively coupled to first and second qubits via respective first and second drive lines. The biasing component can facilitate dynamic control of ZZ interactions between the first and second qubits using continuous wave (CW) tones applied via the respective first and second drive lines.

Drive enhanced J/ZZ operation for superconducting qubits

Techniques regarding resetting highly excited qubits are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a reset component that can de-excite a qubit system to a target state by transitioning a population of a first excited state of the qubit system to a ground state and by applying a signal to the qubit system that transitions a population of a second excited state to the first excited state.

Qubit reset from excited states

Systems and techniques that facilitate qubit pulse calibration via canary parameter monitoring are provided. In various embodiments, a system can comprise a measurement component that can measure a canary parameter associated with a qubit control channel. In various embodiments, the system can further comprise a scaling component that can modify a plurality of parameters associated with the qubit control channel via a scaling factor. In various cases, the scaling factor can be based on the canary parameter. In various embodiments, the canary parameter can be a rotation error of a qubit driven by a microwave pulse transmitted along the qubit control channel. In various embodiments, the plurality of parameters can be amplitudes of a plurality of microwave pulses transmitted along the qubit control channel. In various embodiments, the plurality of parameters can be phases of a plurality of microwave pulses transmitted along the qubit control channel.

Qubit pulse calibration via canary parameter monitoring

Techniques facilitating dynamic control of ZZ interactions for quantum computing devices. In one example, a quantum coupling device can comprise a biasing component that is operatively coupled to first and second qubits via respective first and second drive lines. The biasing component can facilitate dynamic control of ZZ interactions between the first and second qubits using off-resonant microwave signals applied via the respective first and second drive lines.

All microwave ZZ control

Field effect transistors and methods of forming the same include forming a stack of nanosheets of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.

Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETS

A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer

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Yorktown Heights, NY, United States of America

Isaac Lauer