Hughes Aircraft Company

Rockwell International Corporation

The United States of America As Represented by the Administrator of the

Other

Technology Service Corporation

Johnson-grace

Truong, T.k./ Chen, T.c.

Irving S Reed

Trieu-Kie Truong

In-Shek Hsu

Irving Sperling

Leslie J Deutsch

Peter Swerling

Tsen Chung Cheng

Truieu K Truong

Alfred C Yu

Oliver E Drummond

Piyapong Thanyasrisung

T K Truong

Lawrence E Brennan

Lung J Wang

William A Bundy

Xuemin Chen

J Scott Goldstein

Wen S Hsieh

Xiaowei Yin

The present invention discloses an adaptive near-far resistant receiver for wireless communication systems, such as, asynchronous DS-CDMA systems, without the use of prior synchronization. The only requirement is knowledge of the spreading code of the desired user. Also there is no need of a training period or of data-free observations. In one aspect the present system describes a method and system for filtering of an asynchronous wireless signal comprising the steps of receiving a data vector; of using the received data vector to update the weight coefficients of an adaptive filter without a prior knowledge of synchronization and without a need for a separate training period or data free observations. In another aspect, the present system describes an adaptive near-far resistant receiver for an asynchronous wireless systems comprising means for receiving a data vector; means for; using the received data vector to update weight coefficients of an adaptive filter, and means for iterative multistage decomposition updating of the filter coefficients. In one embodiment the receiver uses an adaptive filter bank comprising a plurality of adaptive filters, wherein each filter corresponds to at least one different sampling time. An estimate of the timing is obtained from the maximum of a set of sequential outputs from the filter bank, The output that yields the maximum is preferably used to demodulate the information bit.

Self-synchronizing adaptive multistage receiver for wireless communication systems

A fast and efficient method and system for computation of cubic-spline interpolation for data compression is described. In one aspect, the present invention is a method and system for defining a cubic-spline filter; correlating the filter with the signal to obtain a correlated signal; autocorrelating the filter to obtain autocorrelated filter coefficients; computing a transform of the correlated signal and the autocorrelated filter coefficients; dividing the transform of the correlated signal by the transform of the autocorrelated filter coefficients to obtain a transform of a compressed signal; and computing an inverse transform of the transform of the compressed signal to obtain the compressed signal. The signal, the filter, and the transforms may be one dimensional or two dimensional. Further, the transforms may be a fast Fourier transform (FFT) or a Winograd discrete Fourier transform (WDFT) with an overlap-save scheme. Also, a zonal filter may be defined to simplify the steps of correlating and autocorrelating.

Fast and efficient computation of cubic-spline interpolation for data compression

A computationally fast, effective method for compressing digital images uses an optimized subsampling process. A set of spatially overlapping spline functions is used as a basis onto which the image data are projected by use of a least-mean-squares criterion. The specified processes can be implemented for compressing and interpolating digital data arrays of N dimensions. Linear, planar and hyperplanar spline functions allow convenient, fast and efficient closed-form optimal compression, which process is easily incorporated into existing digital processing systems. A key advantage of the disclosed method is the fast coding/reconstruction speed, because it involves only FFT or convolution types of processors.

Optimal spline interpolation for image compression

A keyless entry system which employs an identification code for each transmitter, a key sequence number, and a rolling code generated by a polynomial equation ensure unauthorized access. The system provides for resynchronization in the event of battery replacement or power failure. The system accommodates activation of a transmitter and incrementation of the rolling code when it is out of range of the receiver. This system further accommodates replacement of lost or stolen keys with a higher priority key, which then prevents access by the lost or stolen transmitter.

Keyless entry system using a rolling code

A vehicle access transmitter and receiver pair which cooperate to implement a code transmission strategy which requires a minimum amount of energy thereby accomplishing maximum battery life while achieving operations secure from unauthorized access. The transmitter produces a string of start-and-stop pulse pairs which are each spaced in a timed interval so as to represent unique values. In operation the transmitter generates a sequence of four start-and-stop pulses with the duration of start-and-stop pulse pair proportional to the respective key code. The receiver detects the pulses and supplies them to a code comparison circuit. A lock code is stored and supplied to the code comparison circuit. During the reception time between each start-and-stop pulse in a pair, the demodulator counts up sequentially producing a vector sum of the lock code and the received code value. If the vector sum of all code valves stored and received equals zero, then a VALID signal is generated by the code comparison circuit permitting access to the vehicle via the selected path, i.e., Door, Trunk, etc.

Secure remote control system

A clutter rejection filter for use in detecting moving targets which may be employed in a passive optical acquisition system. The filter comprises a plurality of detector elements which view an image scene. A plurality of transversal filters are individually coupled to the plurality of detector elements. Each of the transversal filters amplitude weight signals provided by the respective detector elements as a function of time, with each of the transversal filters having a predetermined impulse response. Summing circuitry is coupled to each of the transversal filters for combining the output signals provided thereby into a single output signal for the filter. The filter provides output signals which are maximized for objects traveling at a first velocity and minimized for objects traveling at a second velocity.

Vector filter for optical moving target detection

Am image processing method which is adapted for use in a system having memory for storing in a planar array a plurality of output data samples from a scanning image detector. The invention generates first and second hexagonal sampling patterns within a window on the array. The hexagonal sampling patterns include a first set of data samples with a plurality of peripheral data samples, defining each hexagon, and a data sample at the center of the hexagon. The first and second hexagonal sampling lattices share a common data sample. The generation of the hexagonal sampling patterns is achieved by timing the sampling of the scanning image detectors. A weight is assigned to each data sample within each of the hexagonal sampling lattices and performs a convolution operation on the hexagons to provide a final value for assignment to the common data sample.

Method and apparatus for sampling lattice pattern generation and

A concatenated coding system consisting of a (255,223) Reed-Solomon outer code and a convolutional inner code is provided with either a block of preinterleaved frames or an interleaver of frames in a block of data symbols to be coded in the outer decoder. By interleaving, errors are constrained to occur in only one symbol in a frame, which can be corrected by the Reed-Solomon outer decoder. After transmission and inner decoding, the data symbols are deinterleaved for outer decoding. Instead of preinterleaving at the source, or interleaving before inner encoding, the frames of data symbols may be interleaved at the receiver after inner decoding and then combined with the inner decoded check symbols for outer decoding. The outer encoder is a bit-serial Reed-Solomon encoder with programmable interleaving, and the inner decoder is a Viterbi decoder.

VLSI single-chip (255,223) Reed-Solomon encoder with interleaver

A pipeline binary updown counter is comprised of simple stages that may be readily replicated. Each stage is defined by the Boolean logic equation

VLSI binary updown counter

In a system for reducing sidelobes in adaptive receiving array antennas, an auxiliary signal is radiated through an omnidirectional antenna collocated with the phase center of an adaptive array antenna. The auxiliary signal is so transmited as to form a probe or pilot beam with a notch in the main-beam direction by transmitting through both the omnidirectional and the array antenna simultaneously. The relative phases of both antennas are controlled to obtain near-zero radiation in the main-beam direction. Adaptive control loops receive returns from the probe beam and adjust the weights of the receiving array antenna. The receiving array weights are used to form a low sidelobe antenna pattern for reception of the main radar signal, which is transmitted with a directional pattern. Either time or frequency separation may be used to distinguish the probe beam from the main beam.

Growing community of inventors

Santa Monica, CA, United States of America

Irving S Reed