Intel Corporation

Iris Sorani

Alon Naveh

Eliezer Weissmann

Zeev Offen

Itamar S Kazachinsky

Yair Kazarinov

Geoffrey S Strongin

Ittai Anati

Joseph Nuzman

Shlomo Raikin

Gideon Gerzon

Larisa Novakovsky

Hisham Shafi

Alex Berenzon

Gur Hildesheim

An apparatus is described. The apparatus includes a cache memory having two or more memory blocks and a central processing unit (CPU), coupled to the cache memory, to open a first memory block within the cache memory upon exiting from a low power state.

Cache memory staged reopen

A processor of an aspect includes operation mode check logic to determine whether to allow an attempted access to an operation mode and access type protected memory based on an operation mode that is to indicate whether the attempted access is by an on-die processor logic. Access type check logic is to determine whether to allow the attempted access to the operation mode and access type protected memory based on an access type of the attempted access to the operation mode and access type protected memory. Protection logic is coupled with the operation mode check logic and is coupled with the access type check logic. The protection logic is to deny the attempted access to the operation mode and access type protected memory if at least one of the operation mode check logic and the access type check logic determines not to allow the attempted access.

Access type protection of memory reserved for use by processor logic

A method and apparatus for monitor and mwait in a distributed cache architecture is disclosed. One embodiment includes an execution thread sending a MONITOR request for an address to a portion of a distributed cache that stores the data corresponding to that address. At the distributed cache portion the MONITOR request and an associated speculative state is recorded locally for the execution thread. The execution thread then issues an MWAIT instruction for the address. At the distributed cache portion the MWAIT and an associated wait-to-trigger state are recorded for the execution thread. When a write request matching the address is received at the distributed cache portion, a monitor-wake event is then sent to the execution thread and the associated monitor state at the distributed cache portion for that execution thread can be reset to idle.

Method and apparatus for monitor and MWAIT in a distributed cache architecture

Method and apparatus for MONITOR and MWAIT in a distributed cache architecture

Embodiments of the present invention provide an apparatus, system, and method of generating an execution instruction. Some demonstrative embodiments my include generating an execution instruction of a predetermined executable format based on memory address data of a memory-access instruction representing a memory address. Other embodiments are described and claimed.

Device, system and method of generating an execution instruction based on a memory-access instruction

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Nahariya, Israel

Iris Sorani