Sandisk Technologies Inc.

Iris Lu

Tai-Yuan Tseng

Ohwon Kwon

Chia-Kai Chou

Yan Li

Kou Tei

Kei Akiyama

Kei Kitamura

Yonggang Wu

Yoshito Katano

Techniques are presented to reduce sense amplifier noise from parasitic capacitances that can affect the internal transfer of a data value from a data latch to a sensing node. To transfer the data value, the sensing node is pre-charged and the data value used to set the control gate voltage on a transistor in a discharge path for the sensing node. In the discharge path, the transistor is connected in series with a switch, so that when the switch is turned on, the data value on the transistor's control gate will determine whether or not the sensing node discharges. To reduce noise in the process, before the data value is used to bias the discharge path transistor's control gate, a node between the transistor and switch is charged. Additionally, a lower voltage level can be used to turn on the discharge path switch.

Noise reduction in sense amplifiers for non-volatile memory

An apparatus is provided that includes a memory structure including non-volatile memory cells, a first processor and a second processor. The first processor is configured to provide a plurality of sets of commands to a second processor to perform memory operations on the non-volatile memory cells. The second processor is configured to execute the sets of commands and provide a control signal to the first processor. The first processor is further configured to provide the sets of commands to the second processor based on a status of the control signal. The second processor is further configured to control the status of the control signal so that the second processor executes sets of commands with no idle time between consecutive sets of commands.

Apparatus and methods for back-to-back state machine controller bus operations

Apparatuses and techniques are described for reducing the number of latches used in sense circuits for a memory device. The number of internal user data latches in a sense circuit is reduced by using an external data transfer latch to store a bit of user data, in place of an internal user data latch. The user data in the data transfer latches identifies a subset of the data states which are not prohibited from having a verify test. The subset is shifted as the program operation proceeds, at specified program loops, to encompass higher data states. The completion of programming by a memory cell is indicated by the user data latches and another internal latch of the sense circuit in place of the external data transfer latch.

Window program verify to reduce data latch usage in memory device

A non-volatile memory device includes a control circuit configured to connect to a bit line that is connected to one or more non-volatile memory cells. The control circuit includes a first plurality of data latches connected to a first local data bus to store first program-verify pass/fail bits and a second plurality of data latches connected to a second local data bus to store second program-verify pass/fail bits for second non-volatile memory cells. The non-volatile memory device further includes a shared isolation latch and one or more interface circuits connected to the first local data bus and the second local data bus. The one or more interface circuits are configured to selectively block the first program-verify pass/fail bits from the first plurality of latches and the second program-verify pass/fail bits from the second plurality of latches according to an indicator bit stored in the shared isolation latch.

Non-volatile memory with isolation latch shared between data latch groups

A local data bus of a sense amplifier associated with one bit line is used to perform logical operations for a sensing operation performed by another sense amplifier associated with a different bit line. Each sense amplifier circuit includes a sensing node that is pre-charged, then discharged through a selected memory cell and a local data bus with a number of data latches connected. Target program data can be stored in the latches and combined in logical combinations with the sensed value of the memory cell to determine whether it has verified. By including a transfer circuit between the local data buses of a pair of sense amplifiers, the logical operations of a first sense amplifier can be performed using the local data bus of the paired sense amplifier, freeing the first sense amplifier's sense node to be concurrently pre-charged for a subsequent sensing operation, thereby improving performance.

Sense amplifier structure for non-volatile memory with neighbor bit line local data bus data transfer

Read and write circuitry, described herein, comprises data latches, each data latch connected to a bit line and arranged in a same column as the bit line; and transfer latches, each transfer latch connected to a data latch and arranged in a same column as the data latch. Further, circuitry described herein is configured to: transfer a word to and from the transfer latches of a first column and the subset of transfer latches of a second column; transfer a first portion of the word between the transfer latches of the first column and data latches of the first column that are connected to the transfer latches of the first column; and transfer a second portion of the word between the subset of transfer latches and data latches of the second column that are connected to the subset of transfer latches.

Transfer latch tiers

Technology is disclosed herein for testing circuitry that controls memory operations in a memory structure having non-volatile memory cells. The testing of the circuitry can be performed without the memory structure. The memory structure may reside on one semiconductor die, with sense blocks and a control circuit on another semiconductor die. The control circuit is able to perform die level control of memory operations in the memory structure. The control circuit may control the sense blocks to simulate sensing of non-volatile memory cells in the memory structure even though the sense blocks are not connected to the memory structure. The control circuit verifies correct operation of the semiconductor die based on the simulated sensing. For example, the control circuit may verify correct operation of a state machine that controls sense operations at a die level. Thus, the operation of the semiconductor die may be tested without the memory structure.

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Fremont, CA, United States of America

Iris Lu