Vmware, Inc.

Graft, Inc.

Irina Calciu

Pratap Subrahmanyam

Jayneel Gandhi

Aasheesh Kolli

Andreas Georg Nowatzyk

Venkata Subhash Reddy Peddamallu

Rajesh Venkatasubramanian

Marcos Kawazoe Aguilera

Kiran Tati

Isam Wadih Akkawi

Xavier Deguillard

Qasim Ali

Eric Schkufza

Yi Yao

Adam Jamison Oliner

Brian Calvert

Maria Kazandjieva

Mher Hakobyan

Michael Wei

Nadav Amit

Lalith Suresh

Vijaychidambaram Velayudhan Pillai

Adarsh Seethanadi Nayak

Nishchay Dua

Stanko Novakovic

Himanshu Chauhan

Onur Mutlu

Pradeep Fernando

Daniel Woolridge

While an application or a virtual machine (VM) is running, a device tracks accesses to cache lines to detect access patterns that indicate security attacks, such as cache-based side channel attacks or row hammer attacks. To enable the device to detect accesses to cache lines, the device is connected to processors via a coherence interconnect, and the application/VM data is stored in a local memory of the device. The device collects the cache lines of the application/VM data that are accessed while the application/VM is running into a buffer and the buffer is analyzed for access patterns that indicate security attacks.

Coherence-based attack detection

A method of prefetching memory pages from remote memory includes detecting that a cache-line access made by a processor executing an application program is an access to a cache line containing page table data of the application program, identifying data pages that are referenced by the page table data, initiating a fetch of a data page, which is one of the identified data pages, and starting a timer. If the fetch completes prior to expiration of the timer, the data page is stored in a local memory. On the other hand, if the fetch does not complete prior to expiration of timer, a presence bit of the data page in the page table data is set to indicate that the data page is not present.

Smart prefetching for remote memory

A device tracks accesses to pages of code executed by processors and modifies a portion of the code without terminating the execution of the code. The device is connected to the processors via a coherence interconnect and a local memory of the device stores the code pages. As a result, any requests to access cache lines of the code pages made by the processors will be placed on the coherence interconnect, and the device is able to track any cache-line accesses of the code pages by monitoring the coherence interconnect. In response to a request to read a cache line having a particular address, a modified code portion is returned in place of the code portion stored in the code pages.

Coherence-based dynamic code rewriting, tracing and code coverage

A device is connected via a coherence interconnect to a CPU with a cache. The device monitors cache coherence events via the coherence interconnect, where the cache coherence events relate to the cache of the CPU. The device also includes a buffer that can contain representations, such as addresses, of cache lines. If a coherence event occurs on the coherence interconnect indicating that a cache line in the CPU's cache is dirty, then the device is configured to add an entry to the buffer to record the dirty cache line.

Using cache coherent FPGAS to track dirty cache lines

A non-transitory computer readable storage medium has instructions executed by a processor to receive from a network connection different sources of unstructured data, where the unstructured data has multiple modes of semantically distinct data types and the unstructured data has time-varying data instances aggregated over time. An entity combining different sources of the unstructured data is formed. A representation for the entity is created, where the representation includes embeddings that are numeric vectors computed using machine learning embedding models. These operations are repeated to form an aggregation of multimodal, time-varying entities and a corresponding index of individual entities and corresponding embeddings. Proximity searches are performed on embeddings within the index.

Apparatus and method for aggregating and evaluating multimodal, time-varying entities

A non-transitory computer readable storage medium has instructions executed by a processor to receive from a network connection different sources of unstructured data. An entity is formed by combining one or more sources of the unstructured data, where the entity has relational data attributes. A representation for the entity is created, where the representation includes embeddings that are numeric vectors computed using machine learning embedding models, including trunk models, where a trunk model is a machine learning model trained on data in a self-supervised manner. An enrichment model is created to predict a property of the entity. A query is processed to produce a query result, where the query is applied to one or more of the entity, the embeddings, the machine learning embedding models, and the enrichment model.

Apparatus and method for transforming unstructured data sources into both relational entities and machine learning models that support structured query language queries

In a computer system, a processor and an I/O device controller communicate with each other via a coherence interconnect and according to a cache coherence protocol. Registers of the I/O device controllers are mapped to the cache coherent memory space to allow the processor to treat the registers as cacheable memory. As a result, latency of processor commands executed by the I/O device controller is decreased, and size of data stored in the I/O device controller that can be accessed by the processor is increased from the size of a single register to the size of an entire cache line.

Low latency host processor to coherent device interaction

Techniques for achieving application high availability via application-transparent battery-backed replication of persistent data are provided. In one set of embodiments, a computer system can detect a failure that causes an application of the computer system to stop running. In response to detecting the failure, the computer system can copy persistent data written by the application and maintained locally at the computer system to one or more remote destinations, where the copying is performed in a manner that is transparent to the application and while the computer system runs on battery power. The application can then be restarted on another computer system using the copied data.

Application high availability via application transparent battery-backed replication of persistent data

Memory pages of a local application program are prefetched from a memory of a remote host. A method of prefetching the memory pages from the remote memory includes detecting that a cache-line access made by a processor executing the local application program is an access to a cache line containing page table data of the local application program, identifying data pages that are referenced by the page table data, and fetching the identified data pages from the remote memory and storing the fetched data pages in a local memory.

A method of performing a copy-on-write on a shared memory page is carried out by a device communicating with a processor via a coherence interconnect. The method includes: adding a page table entry so that a request to read a first cache line of the shared memory page includes a cache-line address of the shared memory page and a request to write to a second cache line of the shared memory page includes a cache-line address of a new memory page; in response to the request to write to the second cache line, storing new data of the second cache line in a second memory and associating the second cache-line address with the new data stored in the second memory; and in response to a request to read the second cache line, reading the new data of the second cache line from the second memory.

Coherence-based cache-line Copy-on-Write

Disclosed are embodiments for migrating a virtual machine (VM) from a source host to a destination host while the virtual machine is running on the destination host. The system includes an RDMA facility connected between the source and destination hosts and a device coupled to a local memory, the local memory being responsible for memory pages of the VM instead of the source host. The device is configured to copy pages of the VM to the destination host and to maintain correct operation of the VM by monitoring coherence events, such as a cache miss, caused by the virtual machine running on the destination host. The device services these cache misses using the RDMA facility and copies the cache line satisfying the cache miss to the CPU running the VM. The device also tracks the cache misses to create an access pattern that it uses to predict future cache misses.

Using cache coherent FPGAS to accelerate post-copy migration

The disclosure provides an approach for testing if a cache line of a cache has been flushed to non-volatile memory (NVM). The approach generally includes reading, by a central processing unit (CPU), data from the NVM. The approach further includes storing, by the CPU, a copy of the data in the cache as a cache line. The approach further includes modifying, by the CPU, at least a portion of the copy of the data in the cache. The approach further includes requesting, by the CPU, the cache line be flushed to the NVM. The approach further includes performing, by the CPU, one or more instructions in parallel to the cache line being flushed to the NVM. The approach further includes requesting, by the CPU, a state of the cache line and determining if the cache line has been persisted in the NVM based on the state of the cache line.

Cache line persistence indicator for non-volatile memory using coherence states

Disclosed is a method for performing write-back operations to maintain coherence of remote memories in a memory pool. When a local application makes a request for a page of memory that is in the memory pool but not local, a device obtains the page through its RDMA facility and thereafter keeps track of the page for any changes made by the application to the page by storing the page locally and monitoring cache coherency events of cache lines that make up the page. If a requested page become dirty, then periodically the dirty cache lines of the dirty page are written back to the remote memory from which the pages were obtained. In addition, all dirty cache lines are written back when the local memory storing the page becomes full or the application closes a region containing the page.

Using cache coherent FPGAS to accelerate remote memory write-back

Described herein is a method for tracking changes to memory locations made by an application. In one embodiment, the application decides to start tracking and sends a list of virtual memory pages to be tracked to an operating system via an interface. The operating system converts the list of virtual memory pages to a list of physical addresses and sends the list of physical addresses to a hardware unit which performs the tracking by detecting write backs on a coherence interconnect coupled to the hardware unit. After the application ends tracking, the application requests a list of dirty cache lines. In response to the request, the operating system obtains the list of dirty cache lines from the hardware unit and adds the list to a buffer that the application can read. In other embodiments, the operating system can perform the tracking without the application making the request.

Growing community of inventors

Palo Alto, CA, United States of America

Irina Calciu