Altera Corporation

Cypress Semiconductor Corporation

Semiconductor Components Industries, LLC

Alterm Corporation

Irfan Rahim

Jeffrey T Watt

Andy Louie Lee

Jun Liu

Peter John McElheny

William Bradley Vest

Albert Ratnakumar

Bruce B Pedersen

Qi Xiang

Yanzhong Xu

Srinivas Perisetty

Lakhbeer Singh Sidhu

Myron Wai Wong

Shih-Lin S Lee

Jeffrey Xiaoqi Tung

Lin-Shih Liu

Mark Chan

Yow-Juang W Liu

David Lewis

Raminda U Madurawe

Michael David Hutton

Vaughn Betz

Cheng-Hsiung Huang

Shankar Sinha

Lu Zhou

Richard G Cliff

John E Turner

Ping-Chen Liu

John C Costello

Chih-Ching Shih

Yow-Juang Bill Liu

Fangyun Richter

Stephanie T Tran

Guu Lin

Bradley Jensen

Hugh Sung-Ki O

Girish Venkitachalam

Madhuri Mailavaram

Mao Du

Sergey Velichko

Boon Jin Ang

Victor Lenchenkov

Rafael Czernek Camarota

John Eugene Berg

Thow Pang Chong

Yowjuang (Bill) Liu

Ross F Jatou

Oswald L Skeete

Cheng H Huang

Yow-Juang (Bill) Liu

Hamid Soleimani

Eric Choong-Yin Chang

Priya Selvaraj

Peter Mcelheny

Yanzhong Yu

Sriram Muthukumar

Susan Falk

Veenu Shekhar

Implementations of sensing devices may include a plurality of electromagnetic radiation sensing sections coupled to a flexible interconnect and one or more digital sections coupled to the flexible interconnect. The plurality of electromagnetic radiation sensing sections may be self-aligned through the flexible interconnect.

Flexible interconnect sensing devices and related methods

In one embodiment, a method of forming a semiconductor device may include extending a gate conductor of a transistor to overlie a boundary of a well region in which the transistor is formed. The gate conductor may extend to make electrical contact with a gate conductor of a 2nd transistor that is formed external to the well region. A contact conductor may be applied to electrically and physically contact the first and 2nd gate conductors and to also overlie the boundary of the well region.

Method of forming a semiconductor device

An integrated circuit die may include bottom-gate thin-body transistors. The bottom-gate thin-body transistors may be formed in a thinned-down substrate having a thickness that is defined by shallow trench isolation structures that provide complete well isolation for the transistors. The transistors may include gate terminal contacts formed through the shallow trench isolation structures, bulk terminal contacts that are formed through the thinned substrate and that overlap with the gate contacts, and source-drain terminal contacts with in-situ salicide. Additional metallization layers may be formed over the gate/bulk/source-drain contacts after bonding.

Bottom-gate thin-body transistors for stacked wafer integrated circuits

Visual and near infrared pixels may have deep photodiodes to ensure sufficient capture of light. The pixels may have a silicon layer that is etched to form a microlens for the pixel. The pixels may include an inversion layer formed over the silicon layer to prevent dark current. Additionally, the pixels may include a conductive layer formed over the inversion layer that further prevents dark current. The conductive layer may be coupled to a bias voltage supply line. The conductive layer may be biased during image acquisition to prevent dark current. During readout, the bias voltage may be pulsed at a lower voltage to ensure all of the collected charge is transferred out of the photodiode during charge transfer.

Pixels for high performance image sensor

An imaging system may be formed from multiple stacked wafers. A first wafer may include backside illuminated photodiodes, floating diffusion regions, and charge transfer gate structures. The first wafer may be bonded to a second wafer that includes pixel trunk transistors such as reset transistors, source-follower transistors, row-select transistors and associated logic circuits. The pixel trunk transistors may be formed using bottom-gate thin-body transistors. The first and second wafers may share the same backend metallization layers. The second wafer may further be bonded to a third wafer that includes digital signal processing circuits. The digital signal processing circuits may also be implemented using bottom-gate thin-body transistors. Additional metallization layers may be formed over the third wafer. The first, second, and third wafers may be fabricated using the same or different technology nodes.

Monolithically stacked image sensors

Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity.

Memory elements with relay devices

Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Integrated circuits with asymmetric and stacked transistors

In an exemplary embodiment, an apparatus includes a first set of circuit elements and a second set of circuit elements. The first set of circuit elements is used in a first configuration of the apparatus, and the second set of circuit elements is used in a second configuration of the apparatus. The first configuration of the apparatus is switched to the second configuration of the apparatus in order to improve reliability of the apparatus.

Apparatus for improving reliability of electronic circuitry and associated  methods

Power supply decoupling capacitors are provided for integrated circuits. The decoupling capacitors may be distributed in clusters amongst powered circuit components. Each cluster may contain a number of individual capacitor cells that are connected in parallel. Each capacitor cell may contain a capacitor and a resistor connected in series with the capacitor. The capacitors may be metal-insulator-metal (MIM) capacitors. The resistor in each cell may limit the current through an individual capacitor in the event of a short in the capacitor due to a dielectric defect.

Integrated circuit decoupling capacitors

Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. Each memory element may each have four inverter-like transistor pairs that form a bistable element, a pair of address transistors, and a pair of relatively weak transistors connected between two of the inverters that create a common output node which is resistant to rapid changes to its state. The transistors may be connected in a pattern that forms a bistable memory element that is resistant to soft error upset events due to radiation strikes. Data may be loaded into and read out of the memory element using the address transistor pair.

Memory elements with soft error upset immunity

Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions may produce output signals. The integrated circuit may include interconnects that route selected output signals throughout the integrated circuit. The integrated circuit may include output selection circuitry having output selection and interconnect selection stages. The output selection circuitry may be configured to select which of the output signals produced by the programmable logic regions are provided to the interconnects for routing. The interconnect selection stage may be formed using multiplexing circuits or tristate drivers. Logic design system computing equipment may be used to generate configuration data that can be used to program the output selection circuitry to reduce crosstalk by routing signals away from critical interconnects or by double-driving critical interconnects.

Integrated circuits with interconnect selection circuitry

A method that includes using a PMOS pass gate to couple a first line to a second line, where a gate terminal of the PMOS pass gate is coupled to an output terminal of a memory cell, is described. In one implementation, the PMOS pass gate has a negative threshold voltage. In one implementation, the first line and the second line are respectively first and second interconnect lines of an IC.

Method of using a PMOS pass gate

A memory circuit that includes a memory storage unit and access transistors coupled to the memory storage unit, where the access transistors include PMOS transistors, is described. In one implementation, the memory circuit further includes a bias clamp transistor coupled to the memory storage unit.

Memory circuit with PMOS access transistors

Asymmetric transistors such as asymmetric pass transistors may be formed on an integrated circuit. The asymmetric transistors may have gate structures. Symmetric pocket implants may be formed in source-drains on opposing sides of each transistor gate structure. Selective heating may be used to asymmetrically diffuse the implants. Selective heating may be implemented by patterning the gate structures on a semiconductor substrate so that the spacing between adjacent gate structures varies. A given gate structure may be located between first and second adjacent gate structures spaced at different respective distances from the given gate structure. A larger gate structure spacing leads to a greater substrate temperature rise than a smaller gate structure spacing. The pocket implant diffuses more in portions of the substrate with the greater temperature rise, producing asymmetric transistors. Asymmetric pass transistors may be controlled by static control signals from memory elements to implement circuits such as programmable multiplexers.

Integrated circuits with asymmetric pass transistors

Growing community of inventors

Milpitas, CA, United States of America

Irfan Rahim