Motorola Corporation

Semiconductor Components Industries, LLC

Irenee M Pages

Patrice M Parris

Jeffrey Pearse

Barbara Vasquez

Yee-Chaung See

Juan Buxo

Hak-Yam Tsoi

E James Prendergast

Edouard De Fr&eacute;sart

Rainer Thoma

Quang X Nguyen

Thierry Michel Sicard

Denis Griot

Cynthia Trigas

Henri Gay

Eric Scott Carman

Quang Xuan Nguyen

A vertically diffused FET ( ) is fabricated on a semiconductor die ( ) that includes an N substrate ( ) and an N epitaxial layer ( ). The FET ( ) has a source region ( ) and a channel region ( ) near a front surface ( ) of the epitaxial layer ( ), and a drain region in the substrate ( ). A trench ( ) extends through the epitaxial layer ( ) to the substrate ( ). A conductive layer ( ) fills the trench ( ), thereby forming a conductive plug ( ) electrically coupled to the substrate ( ). The conductive plug ( ) forms a top side drain electrode of the FET ( ).

Semiconductor device and method for fabricating the same

A single level gate NVM device (20) includes a floating gate FET (11) and a capacitor (12) fabricated in two P-wells (27, 28) formed in an N-epitaxial layer (22) on a P-substrate (21). P+ sinkers (29, 31) and N-type buried layers (25, 26) provide isolation between the two P-wells (27, 28). The NVM device (20) is programmed or erased by biasing the FET (11) and the capacitor (12) to move charge carriers onto or away from a conductive layer (36) which serves as a floating gate (14) of the FET (11). Data is read from the NVM device (20) by sensing a current flowing in the FET (11) while applying a reading voltage to the capacitor (12).

Single level gate nonvolatile memory device and method for accessing the

A multiple output, vertical MOSFET device (11) with improved electrical performance and thermal dissipation is integrated with an additional semiconductor device or semiconductor circuit (18) on a single semiconductor substrate (34). The method of making the vertical MOSFET device (11) involves thinning the semiconductor substrate (34) after fabricating the vertical MOSFET device (11) and the semiconductor circuit (18) to reduce the vertical component of electrical and thermal resistance and to increase the thermal dissipation efficiency. Electrical performance is improved by thinning the semiconductor substrate (34) and by providing a low resistivity, patterned metal buried layer. Thermal management is enhanced by using flip chip bumps (24) to dissipate heat from a top surface (31) of the semiconductor substrate (34) and by using the patterned buried metal layer (26) to dissipate heat from a bottom surface (32) of the semiconductor substrate (34).

Vertical MOSFET device having frontside and backside contacts

A method of processing a semiconductor device in which a microwave field is generated to surround the semiconductor device while a focussed electron beam or ion beam is applied to the substrate of the device whereby the presence of the electron or ion beam creates a conductive region which increases the microwave field intensity in that region, so that the intensified microwave field creates a local heating effect in the substrate to perform a local annealing action.

Thermal annealing of semiconductor devices

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Villeneuve Tolosane, France

Irenee M Pages