Advanced Micro Devices Corporation

Iraj Emami

Bhanwar Singh

Charles E May

Richard W Jarvis

Ramkumar Subramanian

Bharath Rangarajan

Khoi A Phan

Jason Phillip Cain

Thomas J Goodwin

Srikanteswara Dakshina-Murthy

Joyce S Oey Hewett

Michael G McIntyre

John Lee Nistler

Alan Bruce Berezin

Harish Kumar Bolla

Qiaolin Zhang

Luigi Capodiece

The disclosed embodiments reduce across-chip performance variation through non-contact electrical metrology. According to a feature is a process control system that includes a component that measures transistor electrical performance in a product wafer. Also included in the system is a mapping component that converts the transistor performance into exposure dose values and a process tool that communicates the exposure dose value to a scanner. The exposure dose value is fed back for optimization of future chip exposures. The disclosed embodiments directly optimize transistor performance, thus controlling an important parameter in many integrated circuits.

Scanner optimization for reduced across-chip performance variation through non-contact electrical metrology

The claimed subject matter can provide a mechanism for ascertaining a variety of metrological data relating to one or more features (e.g., a transistor gate) of a chip/wafer. In addition, results of electrical testing on the chip/wafer can also be gathered and, together with the metrological data, input to a data store. From the information in the data store, a three-dimensional model for the feature(s) of the chip/wafer can be constructed and subjected to analysis, testing, and/or simulation. As well, the three-dimensional model can be optimized and an optimized three-dimensional model can be employed to affect process control in a feedback/forward manner, e.g., to apply optimizations to the next or the current wafer, respectively. Accordingly, the disclosed mechanisms may be used to optimize semiconductor performance, yield, or for research and development. In addition the three-dimensional model may be used in analysis, simulation, or debugging software.

Transistor gate shape metrology using multiple data sources

A system for optimizing critical dimension uniformity in semiconductor manufacturing processes is provided. The system comprises a bake plate simulator to model a physical bake plate. A finite element analysis engine uses information from the bake plate simulator to calculate missing information. A lithography simulator predicts outcomes of a lithography process using information from the bake plate simulator and the finite element analysis engine. The system can be used in a predictive capacity or as part of a process control system.

Optimizing critical dimension uniformity utilizing a resist bake plate simulator

Systems and/or methods are disclosed for aligning multiple layers of a multi-layer semiconductor device fabrication process and/or system utilizing a composite alignment mark. A component is provided to form the composite alignment mark, such that a first portion of the composite alignment mark is associated with a layer of the wafer and a second portion of the composite alignment mark is associated with a disparate layer of the wafer. An alignment component is utilized to align a reticle for a layer to be patterned to the composite alignment mark.

Composite alignment mark scheme for multi-layers in lithography

Systems and/or methods are disclosed for measuring and/or controlling an amount of impurity that is dissolved within an immersion medium employed with immersion lithography. The impurity can be photoresist from a photoresist layer coated upon a substrate surface. A known grating structure is built upon the substrate. A real time immersion medium monitoring component facilitates measuring and/or controlling the amount of impurities dissolved within the immersion medium by utilizing light scattered from the known grating structure.

Real time immersion medium control using scatterometry

A method is provided for manufacturing, the method including processing a workpiece in a processing step, detecting defect data after the processing of the workpiece in the processing step has begun and forming an output signal corresponding to at least one type of defect based on the defect data. The method also includes feeding back a control signal based on the output signal to adjust the processing performed in the processing step to reduce the at least one type of defect.

Use of contamination-free manufacturing data in fault detection and classification as well as in run-to-run control

A drop-in test structure fabricated upon a production integrated circuit elevational profile and a method for using the drop-in test structure for characterizing an integrated circuit production methodology are described. The test structure may be fabricated upon an integrated circuit elevational profile formed according to a subset of steps within a sequence of steps of the integrated circuit production methodology that culminates in a production integrated circuit intended for use by a consumer. According to an embodiment, the integrated circuit elevational profile may be fabricated according to a majority of the sequence of steps. Alternatively, the integrated circuit elevational profile may be fabricated according to a minority of the sequence of steps. The test structure may be fabricated upon die sites designated to receive the test structure. Alternatively, the test structure may be fabricated upon die sites otherwise intended for operable integrated circuits. In an embodiment, test structures may be fabricated upon only selected die sites. Alternatively, test structures may be fabricated across the entire wafer to characterize spatial variation in process parameters. The test structures may be used to characterize the underlying elevational profile and to identify both systematic and random defects either as part of routine monitoring or in response to the observance of defective chips using other monitoring.

Drop-in test structure and methodology for characterizing an integrated circuit process flow and topography

A test structure which includes alternating grounded and floating conductive lines may be used to test the formation of conductive features on an integrated circuit topography. During irradiation of the conductive lines from an electron source, the grounded conductive lines will appear darker than the floating conductive lines when the test structure is inspected. If a short occurs between the conductive lines, due to an extra material defect, the portion of the floating line in the vicinity of the defect will also appear darkened. If an open appears along a grounded line, the non-grounded portion of the grounded line will be glowing. The grounded conductive lines are preferably grounded through a depletion-mode transistor. By applying a voltage to the transistor, the grounded line may be disconnected from ground, allowing electrical testing of the test structure. The electrical testing may be used to validate the voltage contrast methodology, as well as determine the approximate size of defects formed on the test structure.

Multipurpose defect test structure with switchable voltage contrast capability and method of use

A drop-in test structure fabricated upon a virtual integrated circuit elevational profile and a method for using the drop-in test structure for characterizing an integrated circuit production methodology and integrated circuit fabrication equipment are described. According to an embodiment, the test structure may be fabricated upon an elevational profile corresponding elevationally to a complete or substantially complete production integrated circuit topography. According to an alternative embodiment, the test structure may be fabricated upon an elevational profile corresponding elevationally to a partially complete production topography. The test structure and method may be used to characterize the underlying elevational profile and to identify both systematic and random defects either as part of routine monitoring or in response to the observance of defective chips using other monitoring. The test structure and method may also be used to characterize the effects of intentional modifications to existing processing parameters and equipment and to characterize the performance of new processes and equipment.

Drop-in test structure and abbreviated integrated circuit process flow for characterizing production integrated circuit process flow, topography, and equipment

A test structure which includes alternating grounded and floating conductive lines may be used to test the formation of conductive features on an integrated circuit topography. A number of intentional partial defects may be formed at predetermined locations along the test structure. During irradiation of the conductive lines from an electron source, the grounded conductive lines will appear darker than the floating conductive lines. If a short occurs between the conductive lines, due to an extra material defect, the portion of the floating line in the vicinity of the defect will also appear darkened. If an open appears along a grounded line, the non-grounded portion of the grounded line will be glowing. The grounded conductive lines are preferably grounded through a depletion-mode transistor. By applying a voltage to the transistor, the grounded line may be disconnected from ground, allowing electrical testing of the test structure.

Semiconductor test structure with intentional partial defects and method of use

A method is provided for manufacturing, the method including processing a workpiece in a processing step and detecting defect data after the processing of the workpiece in the processing step has begun. The method also includes filtering the defect data using a fractal filter and forming an output signal corresponding to at least one type of defect based on the fractally filtered defect data. The method further includes feeding back a control signal based on the output signal to adjust the processing performed in the processing step to reduce the at least one type of defect.

Growing community of inventors

Austin, TX, United States of America

Iraj Emami