International Business Machines Corporation

Ira Rosen

Nir Naaman

Ayal Zaks

Dorit Nuzman

Samuel Kallner

Nili Guy

Lior Turgeman

Adar Amir

Alexandre E Eichenberger

Ulrich Weigand

Brian King Flachs

Michael Masin

Shmuel Kalner

Techniques for generating a set of Deep Learning (DL) models are described. An example method includes training an initial set of DL models using the training data, wherein a topology of each of the DL models is determined based on the parameters vector. The method also includes generating a set of estimate performance functions for each of the DL models in the initial set based on the set of edge-related metrics, and generating a plurality of objective functions based on the set of estimated performance functions. The method also includes generating a final DL model set based on the objective functions, receiving a user selection of a selected DL model from the final DL model set, and deploying the selected DL model to an edge device.

Adaptation of deep learning models to resource constrained edge devices

An example system includes a processor to monitor system resources and performance preferences. The processor is to select model fragments based on the system resources and the performance preferences. The processor is to also construct a running artificial intelligence (AI) model from the selected model fragments. The processor is to further automatically modify the running AI model using the model fragments in response to detecting a change in the system resources or a change in the performance preferences.

Modifying artificial intelligence models using model fragments

Methods, systems and computer products for ensuring session correctness for subscribing clients connected to a publish-subscribe broker via a gateway having intermittent connectivity with the broker. The gateway is configured to: (1) subscribe to one or more topics of a publish-subscribe service controlled by the broker in response to one or more subscription sessions initiated by one or more subscribing clients connected to the gateway for subscribing to the topic(s), (2) identify session parameters indicative of activity state of each subscription session, (3) reconnecting to the broker following a disconnection period, (4) receiving from the broker one or more messages published on the topic(s) during the disconnection period, the broker correlates each message with message properties, and (5) publish each message to one or more of the subscribing clients based on compliance of the message properties of the respective message with the session parameters of the respective subscription session.

Enforcing session properties compliance for gateway connected publish-subscribe clients

A compiler of a single instruction multiple data (SIMD) information handling system (IHS) identifies 'if-then-else' statements that offer opportunity for conditional branch conversion. The SIMD IHS employs a processor or processors to execute the executable program. During execution, the processor generates and updates SIMD lane mask information to track and manage the conditional branch loops of the executing program. The processor saves branch addresses and employs SIMD lane masks to identify conditional branch loops with different branch conditions than previous conditional branch loops. The processor may reduce SIMD IHS processing time during processing of compiled code of the original 'if-then-else' statements. The processor continues processing next statements inline after all SIMD lanes are complete, while providing speculative and parallel processing capability for multiple data operations of the executable program.

Management of conditional branches within a data parallel system

A method for vectorization of a block of code is provided. The method comprises receiving a first block of code as input; and converting the first block of code into at least a second block of code and a third block of code. The first block of code accesses a first set of memory addresses that are potentially misaligned. The second block of code performs conditional leaping address incrementation to selectively access a first subset of the first set of memory addresses. The third block of code accesses a second subset of the first set of memory addresses starting from an aligned memory address, simultaneously accessing multiple memory addresses at a time. No memory address belongs to both the first subset and the second subset of memory addresses.

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Haifa, Israel

Ira Rosen