Motorola Corporation

Freescale Semiconductor,inc.

Micrel, Incorporated

Motorla, Inc.

Nxp Usa, Inc.

Ira G Miller

Robert Bruce Davies

Robert N Dotson

Eduardo Velarde

John M Pigott

Douglas Alan Garrity

John E Hanna

Thierry Cassagnes

Robert C Rumbaugh

Ricardo Goncalves

Michael W Null

Brett Jason Thompsen

Didier Salle

Geoffrey W Perkins

John J Price

Jaswinder S Jandu

Paul E Fletcher

Ricardo Takase Goncalves

A dual supply level shifter circuit includes a switching circuit and a set of level shifter circuits coupled to the switching circuit. The switching circuit includes a first set of coupled transistors, wherein the supply switching circuit is coupled to a first supply source that is configured to provide a first power supply voltage and is coupled to a second supply source that is configured to provide a second power supply voltage. The set of level shifter circuits includes a second set of coupled transistors, wherein the set of level shifter circuits is configured to receive a voltage input signal at an input node from a first circuit and to supply to an output node of the dual supply level shifter circuit an output signal having a value that is a highest voltage value between the first power supply voltage and the second power supply voltage.

Dual supply level shifter circuits

A switching regulator includes a capacitor, a charge control circuit, a discharge detector, a switch circuit, and a feedback circuit. The charge control circuit charges and discharges the capacitor. The discharge detector has an input coupled to the capacitor to detect when the capacitor has discharged to a predetermined level to indicate an over-current condition. The switch circuit is coupled to receive an input voltage. The switch circuit is made conductive and non conductive by a switching signal for supplying an output voltage at a regulated voltage level. The duty cycle of the switching signal is reduced in response to an indication of an over-current condition. The feedback circuit is for controlling a discharge rate of the capacitor.

Switching regulator with input current limiting capabilities

A circuit comprises a first level shifting circuit. The level shifting circuit comprises a first and second latching differential pairs. The first latching differential pair has first and second inputs for receiving first and second input signals, first and second outputs, and first and second power supply voltage terminals for receiving a first power supply voltage. The second latching differential pair has first and second inputs coupled to the first and second outputs of the first latching differential pair, an output, and first and second power supply voltage terminals for receiving a second power supply voltage, the second power supply voltage being different from the first power supply voltage. In one embodiment, the level shifting circuit protects transistor gates of the circuit from an overvoltage.

Circuit having gate drivers having a level shifter

A driver circuit includes a first and a second voltage rail, a first pre-driver circuit, a power transistor, comparison circuitry which indicates when a voltage level of the first voltage rails is above or below a reference voltage level, a level shift circuit coupled between the first voltage rail and the second voltage rail which provides a level shifted output, a tapered buffer circuit coupled to the first voltage rail and to a first circuit node, wherein the tapered buffer circuit receives the level shifted output and provides a buffered output to a control electrode of the first pre-driver transistor, and a rail voltage adjusting circuit coupled between the first circuit node and the second voltage rail, which, in response to the comparison circuitry indicating that the voltage level of the first voltage rail is above the reference voltage level, adjusts a voltage level of the second voltage rail.

Circuitry in a driver circuit

A current sense device for a power transistor is described. The power transistor is formed in a cellular structure including a cellular array of transistor cells. The current sense device includes multiple transistor cells in the cellular array of transistor cells of the power transistor being used as sense transistor cells. The sense transistor cells are evenly distributed throughout the cellular array where the source terminal of each sense transistor cell is electrically connected to a first node through a metal line in the first metal layer and through a metal line in the second metal layer where the metal lines are electrically isolated from the metal lines connecting the transistor cells of the power transistor. The sense transistor cells measure a small portion of the current flowing through the power transistor based on the size ratio of the current sense device and the power transistor.

Current sensing in a buck-boost switching regulator using integrally embedded PMOS devices

Methods and apparatus for softstarting a voltage regulation circuit. A circuit for generating an output voltage at an output thereof includes a capacitor having a first terminal configured to be coupled to a reference potential and having a second terminal coupled to the output, and a switchable current source coupled to the capacitor for intermittently charging the capacitor until the output voltage is reached.

Clocked ramp apparatus for voltage regulator softstart and method for softstarting voltage regulators

A PWM regulator is operated either a buck mode or a boost mode depending on whether the input voltage is above or below the desired regulated output voltage. The technique uses two sawtooth ramps 180 degrees out of phase. Where the two ramps cross each other is a buck/boost transition level. An error voltage, corresponding to a required duty cycle to achieve a regulated voltage, is compared to the two ramps. The transition from one mode to the other occurs when the error voltage passes the buck/boost transition level of the two ramps. A logic circuit supplies PWM pulses to either buck switching transistors or the boost switching transistors in a power stage of the regulator, depending on the whether the error voltage is above or below the buck/boost transition level, to achieve the regulated voltage.

Buck-boost control logic for PWM regulator

A transconductance amplifier comprising a first input circuit having a first feedback loop; a second input circuit having a second feedback loop; a resistor having a first interface connected to the first input circuit and a second interface connected to the second input circuit; a first differential pair having a first transistor arranged to control current flow in the first feedback loop to maintain a voltage at the first interface of the resistor at substantially a constant voltage relative to an input voltage applied to the first input circuit and a second transistor arranged to control current flow for a first output; and a second differential pair having a third transistor arranged to control current flow in the second feedback loop to maintain a voltage at the second interface of the resistor at substantially a constant voltage relative to an input voltage applied to the second input circuit and a fourth transistor arranged to control current flow for a second output.

Transconductance amplifier

A circuit () is used to perform voltage regulation. In one embodiment, a voltage regulator () is used in conjunction with an output transistor () to form a circuit () which operates to regulate the voltage drop from a first node () to a second node (). This second node () may be used to provide power to circuitry (). The areas of several transistors () in circuit () may be adjusted so that negative and positive temperature coefficients may be balanced such that the circuit () behaves as desired over a range of voltages and temperatures. Note that in one embodiment, circuit () is a 2-terminal device.

Circuit for performing voltage regulation

An analog-to-digital (A/D) converter suitable for use with redundant signed digit (RSD) coverter stages is provided with an out-of-range (OOR) detection circuit. If an out-of-range input signal is detected, the detection circuit identifies the OOR condition so that the converter can take remedial action. Examples of remedial action may include adjusting the gain of one or more converter stages, adjusting the analog input signal provided to one or more converter stages, and/or adjusting the digital output of the converter to reflect the OOR condition. The ORR detection circuit may receive its input from a converter stage that is distinct from the stage providing the most significant bit (MSB) of the digital output to preserve the resolution of the most significant bit.

Methods and apparatus for detecting out-of-range signals in an analog-to-digital converter

A gain stage using switched capacitor architecture and suitable for a pipelined analog to digital converters provides for three pairs of switched capacitor banks whose use may be alternated so as to provide simultaneous sampling of two input channels for sequential gain operation without the interposition of additional circuitry in the signal chain from input to output of the gain stage.

Dual input switched capacitor gain stage

An integrated amplifier that can be use as a standard cell which includes a differential input stage and an output stage to provide an increased input common mode range. The differential input stage includes a pair of differentially configured PMOS transistors coupled to a differential-to-single ended converter comprised of a pair of NMOS transistor. A PNP transistor is formed in the integrated circuit having its base-emitter junction coupled between the drain and gate of one of the NMOS transistors to thereby establish therewith a voltage at the drain of the PMOS device coupled to the inverting input of the amplifier sufficient to maintain the latter in its linear operating range as the input thereto is common moded to ground.

Amplifier stage

An operational amplifier is provided having a null offset that may be digitally adjusted quickly and accurately. The operational amplifier includes a cascode current mirror in an output stage wherein a small portion of current in the cascode current mirror is diverted away into a digitally controlled current divider. The more current that is diverted away, the larger the differential voltage that is created between the inverting and noninverting inputs of the operational amplifier. The current is increased until the output of the operational amplifier switches from the positive supply voltage to the ground supply voltage or vise versa. Additionally, a compensation capacitor at the output of the operational amplifier is switched out of the circuit during adjustment to speed up the null offset adjustment. Because the current being adjusted is not directly at the inputs of the operational amplifier the common mode input range is not deteriorated.

Operational amplifier having improved digitally adjusted null offset

A bandgap voltage reference circuit manufactured with a MOS process is provided which is stable over temperature variations as well as variations in threshold voltage that does not require an operational amplifier. The reference is generated by a MOS current source two sourcing current to substrate bipolar transistors operating at different current densities and operated as emitter followers having a pair MOS current mirrors sinking current therefrom. A start-up circuit initializes the circuit upon application of supply voltages. An output stage multiplies the bandgap reference voltage to the desired output voltage level. A feedback stage improves the accuracy of the output voltage by adjusting the current in the reference circuit.

MOS bandgap voltage reference circuit

A laterally formed PNP transistor includes twenty-four approximately equal area emitters aligned in two rows in spaced relationship, each emitter being adjacent to another emitter and having for collectors formed thereabout to produce ninety-six collector outputs. Certain collectors between adjacent emitters and between rows are merged together with predetermined ones of the collectors associated with different emitter regions being interconnected.

Growing community of inventors

Tempe, AZ, United States of America

Ira G Miller